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MYXN25Q256A13ESF 데이터시트 PDF




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기능 Serial NOR Flash Memory
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MYXN25Q256A13ESF 데이터시트, 핀배열, 회로
Serial NOR Flash Memory
MYXN25Q256A13ESF*
*Advanced information. Subject to change without notice.
256Mb, 3V, Multiple I/O, 4KB Sector Erase
Features
• SPI-compatible serial bus interface
• Double transfer rate (DTR) mode
• 2.7–3.6V single supply voltage
• 108 MHz (MAX) clock frequency supported for all
protocols in single transfer rate (STR) mode
• 54 MHz (MAX) clock frequency supported for all protocols
in DTR mode
• Dual/quad I/O instruction provides increased throughput
up to 54 MB/s
• Supported protocols
ƒƒ Extended SPI, dual I/O, and quad I/O
ƒƒ DTR mode supported on all
• Execute-in-place (XIP) mode for all three protocols
ƒƒ Configurable via volatile or nonvolatile registers
ƒƒ Enables memory to work in XIP mode directly after
power-on
• PROGRAM/ERASE SUSPEND operations
• Continuous read of entire memory via a single command
ƒƒ Fast read
ƒƒ Quad or dual output fast read
ƒƒ Quad or dual I/O fast read
Flexible to fit application
ƒƒ Configurable number of dummy cycles
ƒƒ Output buffer configurable
• Software reset
• 3-byte and 4-byte addressability mode supported
• 64-byte, user-lockable, one-time programmable (OTP)
dedicated area
• Erase capability
ƒƒ Subsector erase 4KB uniform granularity blocks
ƒƒ Sector erase 64KB uniform granularity blocks
ƒƒ Full-chip erase
• Write protection
ƒƒ Software write protection applicable to every 64KB
sector via volatile lock bit
ƒƒ Hardware write protection: protected area size
defined by five nonvolatile bits (BP0, BP1, BP2, BP3,
and TB)
ƒƒ Additional smart protections, available upon request
• Electronic signature
ƒƒ JEDEC-standard 2-byte signature (BA19h)
ƒƒ Unique ID of 17 read-only bytes including:
additional extended device ID (EDID) to identify
device factory options; customized factory data
• Minimum 100,000 ERASE cycles per sector
• More than 20 years data retention
OptionsCode
• Packages: TSOPII
DG
ƒƒ SOP2-16/300milsSF
• Temperature Ranges
ƒƒ Military (-55°C to +125°C)
XT
• Part Marking: Label (L), Dot (D)
MYXN25Q256A13ESF*
Revision 1.2 - 04/4/2016
1
Form #: CSI-D-685 Document 016




MYXN25Q256A13ESF pdf, 반도체, 판매, 대치품
Serial NOR Flash Memory
MYXN25Q256A13ESF*
1.3
1.4
1.5
Operating Protocols
*Advanced information. Subject to change without notice.
The memory can be operated with three different protocols:
• Extended SPI (standard SPI protocol upgraded with dual and quad operations)
• Dual I/O SPI
• Quad I/O SPI
The standard SPI protocol is extended and enhanced by dual and quad operations. In addition, the dual SPI
and quad SPI protocols improve the data access time and throughput of a single I/O device by transmitting
commands, addresses, and data across two or four data lines.
Each protocol contains unique commands to perform READ operations in DTR mode. This enables high data
throughput while running at lower clock frequencies.
XIP Mode
Execute-in-place (XIP) mode allows the memory to be read by sending an address to the device and then
receiving the data on one, two, or four pins in parallel, depending on the customer requirements. XIP mode
offers maximum flexibility to the application, saves instruction overhead, and reduces random access time.
XIP mode requires only an address (no instruction) to output data, improving random access time and
eliminating the need to shadow code onto RAM for fast execution.
Nonvolatile configuration register bits can set XIP mode as the default mode for applications that must enter XIP
mode immediately after powering up.
All protocols support XIP operation. For flexibility, multiple XIP entry and exit methods are available.
Device Configurability
The N25Q family offers additional features that are configured through the nonvolatile configuration register
for default and/or nonvolatile settings. Volatile settings can be configured through the volatile and volatile-
enhanced configuration registers. These configurable features include the following:
• Number of dummy cycles for the fast READ commands
• Output buffer impedance
• SPI protocol types (extended SPI, dual SPI, or quad SPI)
• Required XIP mode
• Enabling/disabling HOLD
• Enabling/disabling wrap mode
MYXN25Q256A13ESF*
Revision 1.2 - 04/4/2016
4
Form #: CSI-D-685 Document 016

4페이지










MYXN25Q256A13ESF 전자부품, 판매, 대치품
3
3.1
Serial NOR Flash Memory
MYXN25Q256A13ESF*
*Advanced information. Subject to change without notice.
Symbol
HOLD#
Type
Control
Input
Description
HOLD: Pauses any serial communications with the device without deselecting the device. DQ1 (output) is High-Z.
DQ0 (input) and the clock are Don't Care. To enable HOLD, the device must be selected with S# driven LOW. HOLD#
is used for input/output during the following operations: QUAD OUTPUT FAST READ, QUAD INPUT/OUTPUT FAST
READ, QUAD INPUT FAST PROGRAM, and QUAD INPUT EXTENDED FAST PROGRAM. In QIO-SPI, HOLD# acts as an
I/O (DQ3 functionality), and the HOLD# functionality is disabled when the device is selected. The HOLD# functionality
can be disabled using bit 4 of the NVCR or bit 4 of the VECR. On devices that include DTR mode capability, the
HOLD# functionality is disabled as soon as a DTR operation is recognized.
Write protect: W# can be used as a protection control input or in QIO-SPI operations. When in extended SPI with
single or dual commands, the WRITE PROTECT function is selectable by the voltage range applied to the signal. If
W#
Control voltage range is low (0V to VCC), the signal acts as a write protection control input. The memory size protected against
Input PROGRAM or ERASE operations is locked as specified in the status register block protect bits 3:0. W# is used as an
input/output (DQ2 functionality) during QUAD INPUT FAST READ and QUAD INPUT/OUTPUT FAST READ operations
and in QIO-SPI.
Supply voltage: If VPP is in the voltage range of VPPH, the signal acts as an additional power supply, as defined in
the AC Measurement Conditions table. During QIFP, QIEFP, and QIO-SPI PROGRAM/ERASE operations, it is possible
to use the additional VPP power supply to speed up internal operations. However, to enable this functionality, it is
VPP Power necessary to set bit 3 of the VECR to 0. In this case, VPP is used as an I/O until the end of the operation. After the
last input data is shifted in, the application should apply VPP voltage to VPP within 200ms to speed up the internal
operations. If the VPP voltage is not applied within 200ms, the PROGRAM/ERASE operations start at standard speed.
The default value of VECR bit 3 is 1, and the VPP functionality for quad I/O modify operations is disabled.
VCC Power Device core power supply: Source voltage.
VSS Ground Ground: Reference for the VCC supply voltage.
DNU – Do not use.
NC – No connect.
Memory Organization
Memory Configuration and Block Diagram
Each page of memory can be individually programmed. Bits are programmed from one through zero. The
device is subsector, sector, or bulk erasable, but not page-erasable. Bits are erased from zero through one.
The memory is configured as 33,554,432 bytes (8bits each); 512 sectors (64KB each); 8192 subsectors (4KB
each); and 131,072 pages (256 bytes each); and 64 OTP bytes are located outside the main memory array.
MYXN25Q256A13ESF*
Revision 1.2 - 04/4/2016
7
Form #: CSI-D-685 Document 016

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Serial NOR Flash Memory

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