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PDF MYXX28HC256 Data sheet ( Hoja de datos )
| Número de pieza | MYXX28HC256 | |
| Descripción | 256Kb EEPROM | |
| Fabricantes | Micross | |
| Logotipo |  |
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256Kb EEPROM
MYXX28HC256
32K x 8 EEPROM - 5 Volt, Byte Alterable
Description
The MYXX28HC256 is a high performance CMOS 32K x 8 E2PROM. It is
fabricated with a textured poly floating gate technology, providing a highly
reliable 5 Volt only nonvolatile memory.
The MYXX28HC256 supports a 128-byte page write operation, effectively
providing a 24ms/byte write cycle and enabling the entire memory to
be typically rewritten in less than 0.8 seconds. The MYXX28HC256 also
features DATA Polling and Toggle Bit Polling, two methods of providing
early end of write detection. The MYXX28HC256 also supports the
JEDEC standard Software Data Protection feature for protecting against
inadvertent writes during power-up and power-down.
Endurance for the MYXX28HC256 is specified as a minimum 100,000
write cycles per byte and an inherent data retention of 100 years.
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
VSS
CerDIP or
Flat PaCcCekreDrDIPIPoror
FlFaltaPt aPcakck
CerSOJ or
CerCLCeCreSCrOSOJ Joror
CCereLrCLCC
1
A21A414
A31A212
4A7A7
5A6A6
6A5A5
7A4A4
8A3A3
9A2A2
1A01A1
11A0A0
III11///OOO23III///012OOO012
V1S4VSSS
28
1 1 27
2 2 26
3 3 25
4 4 24
5 5 23
6 6 22
7 7 21
8 8 20
99
19
1010
18
1111
1212 17
1313 16
1414 15
VCC
2W82E8#
2A71237
2A6826
2A5925
2A41214
2O32E3#
22AC211E22021#
2020
1I/9O197
1I/8O186
1I/7O175
1I/60146
1I/5O153
VCVCCC
WWE#E#
A1A31A36
A8A8A5
A9A9A4
A1A11A1 3
OEO#EA#2
A1A01A01
CEC#EA#0
I/OI/7ON7C
I/OI/I6O/O60
I/OI/5O5
I/0I4/04
I/OI/3O3
4 3 2 1 32 31 30
5 4 4 3 3 2 2 1 132323219313030A8
A66A6 5 5
28 292A99 A8A8
A75A5 6 6
27 282A811 A9A9
A84A4 7 7
26 272N7C A1A111
A93A3
A12A02
A111A1
89M89YX2M8CYMX3Y22XK82C883C23K28K22854
1010
23
262O6E#NCNC
225422AC541E0#OA1EOA0#1E0#
A10A20
NCNC
I/OI1/0O3104
1111 2323 CEC#E#
1115231114123164151175161168171179181281022921192022221022II21//OO76II//OOII//76OO76
CerPGA
CCerePrGPGAA
I/O1 I/O2 I/O3
12 I/OI/1O1 13I/OI/2O2 15I/OI/3O3
1212 1313 1515
I/O0 A0
11 I/OI/0O0 10 A0A0
1111 1010
VSS
14VSVS SS
1414
A1
9 A1A1
99
A2
8 A2A2
88
A3
7
A3A3
A4
6
A4A4
77 66
I/O5
17I/OI/5O5
1717
I/O4
16I/OI/4O4
1616
CE
20CECE
2020
OE
22OEOE
2222
A5
5
A5A5
55
A212A21A2212 2V8C2CV8C2VC8CC
2A429A492A49
I/O6
1I8/OI/6O6
1818
I/O7
1I9/OI/7O7
1919
A10
2A11A0 10
2121
2AA3111A1 11
2323
2A25A8582A58
A6
4
A6A6
44
A7
3
A7A7
33
A114A11A4114
WWE EWE
272727
2A2A616312A3613
Figure 1 - Pin Configuration
MYXX28HC256
Revision 1.4 - 02/13
1
Features
• Access Time (ns): 70, 90, 120, 150
• Simple Byte and Page Write
Single 5V Supply
No External High Voltages or VPP
Control Circuits
Self-Timed
No Erase Before Write
No Complex Programming
Algorithms
No Overerase Problem
• Low Power CMOS:
Active: 60mA
Standby: 500mA
• Software Data Protection
Protects Data Against System Level
Inadvertent Writes
• High Speed Page Write Capability
• Highly Reliable Direct Write™ Cell
Endurance: 100,000 Write Cycles
Data Retention: 100 Years
• Early End of Write Detection
DATA Polling
Toggle Bit Polling
Options
Timing
70 ns access
90 ns access
120 ns access
150 ns access
Packages Ceramic flat pack
CerDIP, 600 mil
CerLCC
CerPGA
CerSOJ
Markings
-7
-9
-12
-15
F
CW
ECA
P
ECJ
Operating Military (-55°C to +125°C) XT
Temp. Industrial (-40°C to +85°C) IT
1 page  
256Kb EEPROM
MYXX28HC256
The Toggle Bit I/O6
Figure 6 - Toggle Bit Bus Sequence
WE#
LAST
WE# WRITE
LAST
WRITE
CE#
CE#
OE#
OE#
I/O6
I/O6
VO*H
VOH
VOL
HIGH Z
*
I/O6
*
beginning
and
ending
VstOaLte
of
I/O6
will
vary.
* I/O6 beginning and ending state of I/O6 will vary.
HIGH Z
*
*
MYXX28HC256
READY
MYXX28HC256
READY
Figure 7 - Toggle Bit Software Flow
LAST WRITE
LAST WRITE
YES
YES
LOAD ACCUM
LOAD ACFCRUOMM ADDR n
FROM ADDR n
COMPARE
COMPAARCECUM WITH
ACCUM WITAHDDR n
ADDR n
The Toggle Bit can eliminate the software housekeeping chore of
saving and fetching the last address and data written to a device
in order to implement DATA Polling. This can be especially helpful
in an array comprised of multiple MYXX28HC256 memories that is
frequently updated. The timing diagram in Figure 6 illustrates the
sequence of events on the bus. The software flow diagram in Figure
7 illustrates a method for polling the Toggle Bit.
COMOKPA?RCEOMOKPA?RENO
YES YES
MYXX28MHCY2X5X628HC256
READY READY
NO
MYXX28HC256
Revision 1.4 - 02/13
5
5 Page 
256Kb EEPROM
MYXX28HC256
Table 5 - Power-Up Timing
Symbol
Parameter
tPUR1
tPUW1
Power-Up to Read
Power-Up to Write
1. This parameter is periodically sampled and not 100% tested.
Table 6 - Capacitance
TA = +25°C; f = 1MHz; VCC = 5V
Symbol
CI/O
CIN
Test
Input/Output Capacitance
Input Capacitance
Table 7 - Endurance and Data Retention
Parameter
Endurance
Data Retention
Min.
100,000
100
Table 8 - AC Conditions of Test
Input Pulse Levels
Input Rise and Fall Times
Input and Output Timing Levels
0V to 3V
5ns
1.5V
Max. Units
100 µs
5 ms
Max. Units
10
pF
6
Conditions
VI/O = OV
VIN = OV
Max. Units
Cycles
Years
Table 9 - Mode Selection
CE# OE# WE#
Mode
I/O Power
LH
L
HL
Read DOUT Active
Write DIN
H X X Standby & Write Inhibit High Z Standby
LX
X
XH
Write Inhibit
MYXX28HC256
Revision 1.4 - 02/13
11
11 Page | ||
| Páginas | Total 23 Páginas | |
| PDF Descargar | [ Datasheet MYXX28HC256.PDF ] | |
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