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PDF SST25PF040C Data sheet ( Hoja de datos )
| Número de pieza | SST25PF040C | |
| Descripción | 4Mbit 3.3V SPI Serial Flash | |
| Fabricantes | Microchip | |
| Logotipo |  |
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SST25PF040C
4 Mbit, 3.3V, SPI Serial Flash
Features
• Single Voltage Read and Write Operations
- 2.3-3.6V
• Serial Interface Architecture
- SPI Compatible: Mode 0 and Mode 3
• High Speed Clock Frequency
- 40MHz
• Dual Input/Output Support
- Fast-Read Dual-Output Instruction (3BH)
- Fast-Read Dual I/O Instruction (BBH)
• Superior Reliability
- Endurance: 100,000 Cycles
- Greater than 20 years Data Retention
• Ultra-Low Power Consumption:
- Active Read Current: 5 mA (typical)
- Standby Current: 5 µA (typical)
- Power-down Mode Standby Current: 3 µA (typical)
• Flexible Erase Capability
- Uniform 4 KByte sectors
- Uniform 64 KByte overlay blocks
• Page Program Mode
- 256 Bytes/Page
• Fast Erase and Page-Program:
- Chip-Erase Time: 250 ms (typical)
- Sector-Erase Time: 40 ms (typical)
- Block-Erase Time: 80 ms (typical)
- Page-Program Time: 4 ms/ 256 bytes (typical)
• End-of-Write Detection
- Software polling the BUSY bit in Status Register
• Hold Pin (HOLD#)
- Suspend a serial sequence without deselecting the device
• Write Protection (WP#)
- Enables/Disables the Lock-Down function of the
status register
• Software Write Protection
- Write protection through Block-Protection bits in
status register
• Temperature Range
- Industrial: -40°C to +85°C
• Packages Available
- 8-lead SOIC (150 mils)
- 8-contact WDFN (5mm x 6mm)
• All devices are RoHS compliant
Product Description
SST25PF040C is a member of the Serial Flash 25
Series family and feature a four-wire, SPI-compatible
interface that allows for a low pin-count package which
occupies less board space and ultimately lowers total
system costs. SPI serial flash memory is manufactured
with proprietary, high-performance CMOS SuperFlash
technology. The split-gate cell design and thick-oxide
tunneling injector attain better reliability and manufac-
turability compared with alternate approaches.
This Serial Flash significantly improve performance
and reliability, while lowering power consumption. The
device writes (Program or Erase) with a single power
supply of 2.3-3.6V. The total energy consumed is a
function of the applied voltage, current, and time of
application. Since for any given voltage range, the
SuperFlash technology uses less current to program
and has a shorter erase time, the total energy con-
sumed during any Erase or Program operation is less
than alternative flash memory technologies.
SST25PF040C is offered in 8-lead SOIC and 8-contact
WDFN packages. See Figure 2-1 for the pin assign-
ments.
2015 Microchip Technology Inc.
DS20005397B-page 1
1 page  
SST25PF040C
3.0 MEMORY ORGANIZATION
The SST25PF040C SuperFlash memory arrays are
organized in 128 uniform 4 KByte sectors, with 8
64 KByte overlay erasable blocks.
FIGURE 3-1:
MEMORY MAP
Number of 64 KByte
Blocks
7
Number of Sectors Top of Memory Block
127
07FFFFH
07F000H
112
070FFFH
070000H
31
01FFFFH
01F000H
1
01FFFFH
16 010000H
15
00FFFFH
00F000H
0
1
001FFFH
001000H
0
000FFFH
000000H
Bottom of Memory Block
20005197 F51.0.eps
4.0 DEVICE OPERATION
SST25PF040C is accessed through the SPI (Serial
Peripheral Interface) bus compatible protocol. The SPI
bus consist of four control lines: Chip Enable (CE#) is
used to select the device, and data is accessed through
the Serial Data Input (SI), Serial Data Output (SO), and
Serial Clock (SCK).
The SST25PF040C supports both Mode 0 (0,0) and
Mode 3 (1,1) of SPI bus operations. The difference
between the two modes, as shown in Figure 4-1, is the
state of the SCK signal when the bus master is in
Stand-by mode and no data is being transferred. The
SCK signal is low for Mode 0 and SCK signal is high for
Mode 3. For both modes, the Serial Data In (SI) is sam-
pled at the rising edge of the SCK clock signal and the
Serial Data Output (SO) is driven after the falling edge
of the SCK clock signal.
FIGURE 4-1:
CE#
MODE 3
SCK MODE 0
SPI PROTOCOL
MODE 3
MODE 0
SI Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
DON'T CARE
MSB
HIGH IMPEDANCE
SO
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
MSB
20005397 F03.0
2015 Microchip Technology Inc.
DS20005397B-page 5
5 Page 
SST25PF040C
5.3 Fast-Read Dual Output (40 MHz)
The Fast-Read Dual-Output (3BH) instruction outputs
data up to 40 MHz from the SIO0 and SIO1 pins. To ini-
tiate the instruction, execute an 8-bit command (3BH)
followed by address bits A23-A0 and a dummy byte on
SI/SIO0. Following a dummy cycle, the Fast-Read
Dual-Output instruction outputs the data starting from
the specified address location on the SIO1 and SIO0
lines. SIO1 outputs, per clock sequence, odd data bits
D7, D5, D3, and D1; and SIO0 outputs even data bits
D6, D4, D2, and D0. CE# must remain active low for the
duration of the Fast-Read Dual-Output instruction
cycle. See Figure 5-3 for the Fast-Read Dual-Output
sequence.
The data output stream is continuous through all
addresses until terminated by a low-to-high transition
on CE#. The internal address pointer will automatically
increment until the highest memory address is
reached. Once the highest memory address is
reached, the address pointer automatically increments
to the beginning (wraparound) of the address space.
For 4 Mbit density, once the data from address location
7FFFFH has been read the next output will be from
address location 000000H.
FIGURE 5-3:
FAST-READ DUAL OUTPUT SEQUENCE
CE#
SCK
MODE 3
MODE 0
0 1 23 456 78
15 16 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55
SIO0
SIO1
24-Bit Address
3B ADD. ADD. ADD.
HIGH IMPEDANCE
Dummy Cycle
X
IO, Switches from Input to Output
642 0642 0642 0642 0
DOUT DOUT DOUT DOUT
75 3 1 75 31 75 31 75 31
MSB MSB MSB MSB
N N+1 N+2 N+3
20005397 F52.0
2015 Microchip Technology Inc.
DS20005397B-page 11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet SST25PF040C.PDF ] | |
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