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PDF SST25WF080 Data sheet ( Hoja de datos )
| Número de pieza | SST25WF080 | |
| Descripción | 8Mbit 1.8V SPI Serial Flash | |
| Fabricantes | Microchip | |
| Logotipo |  |
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Not recommended for new designs. Please
contact Microchip Sales for more details.
8 Mbit 1.8V SPI Serial Flash
SST25WF080
Not Recommended for New Designs
The SST25WF080 is a member of the Serial Flash 25 Series family and features
a four-wire, SPI-compatible interface that allows for a low pin-count package
which occupies less board space and ultimately lowers total system costs.
SST25WF080 SPI serial flash memory is manufactured with SST proprietary,
high-performance CMOS SuperFlash technology. The split-gate cell design and
thick-oxide tunneling injector attain better reliability and manufacturability com-
pared with alternate approaches.
Features
• Single Voltage Read and Write Operations
– 1.65-1.95V
• Serial Interface Architecture
– SPI Compatible: Mode 0 and Mode 3
• High Speed Clock Frequency
– 75 MHz
• Superior Reliability
– Endurance: 100,000 Cycles (typical)
– Greater than 100 years Data Retention
• Ultra-Low Power Consumption:
– Active Read Current: 2 mA (typical @ 33 MHz)
– Standby Current: 5 µA (typical)
• Flexible Erase Capability
– Uniform 4 KByte sectors
– Uniform 32 KByte overlay blocks
– Uniform 64 KByte overlay blocks
• Fast Erase and Byte-Program:
– Chip-Erase Time: 35 ms (typical)
– Sector-/Block-Erase Time: 18 ms (typical)
– Byte-Program Time: 14 µS (typical)
• Auto Address Increment (AAI) Programming
– Decrease total chip programming time over Byte-Pro-
gram operations
• End-of-Write Detection
– Software polling the BUSY bit in Status Register
– Busy Status readout on SO pin
• Reset Pin (RST#) or Programmable Hold Pin
(HOLD#) option
– Hardware Reset pin as default
– Hold pin option to suspend a serial sequence without
deselecting the device
• Write Protection (WP#)
– Enables/Disables the Lock-Down function of the status
register
• Software Write Protection
– Write protection through Block-Protection bits in status
register
• Temperature Range
– Industrial: -40°C to +85°C
• Packages Available
– 8-lead SOIC (150 mils)
– 8-bump XFBGA
• All devices are RoHS compliant
©2012 Silicon Storage Technology, Inc.
www.microchip.com
DS25024C
10/12
1 page  
8 Mbit 1.8V SPI Serial Flash
SST25WF080
Not Recommended for New Designs
Table 1: Pin Description
Symbol
SCK
SI
SO
CE#
WP#
RST#/
HOLD#
VDD
VSS
Pin Name
Serial Clock
Serial Data Input
Serial Data Out-
put
Chip Enable
Write Protect
Reset
Hold
Power Supply
Ground
Functions
To provide the timing of the serial interface.
Commands, addresses, or input data are latched on the rising edge of the clock input,
while output data is shifted out on the falling edge of the clock input.
To transfer commands, addresses, or data serially into the device.
Inputs are latched on the rising edge of the serial clock.
To transfer data serially out of the device.
Data is shifted out on the falling edge of the serial clock.
Flash busy status pin in AAI mode if SO is configured as a hardware RY/BY# pin. See
“End-of-Write Detection” on page 15 for more information.
The device is enabled by a high to low transition on CE#. CE# must remain low for the
duration of any command sequence.
The Write Protect (WP#) pin is used to enable/disable BPL bit in the status register.
To reset the operation of the device and the internal logic. The device powers on with
RST# pin functionality as default.
To temporarily stop serial communication with SPI Flash memory while device is
selected. This is selected by an instruction sequence; see “Reset/Hold Mode” on page 7.
To provide power supply voltage: 1.65-1.95V for SST25WF080
T1.0 25024
©2012 Silicon Storage Technology, Inc.
5
DS25024C
10/12
5 Page 
8 Mbit 1.8V SPI Serial Flash
SST25WF080
Not Recommended for New Designs
Instructions
Instructions are used to read, write (Erase and Program), and configure the SST25WF080. The
instruction bus cycles are 8 bits each for commands (Op Code), data, and addresses. The Write-
Enable (WREN) instruction must be executed prior to Byte-Program, Auto Address Increment (AAI)
programming, Sector-Erase, Block-Erase, Write-Status-Register, or Chip-Erase instructions. The com-
plete instructions are provided in Table 6. All instructions are synchronized off a high-to-low transition
of CE#. Inputs will be accepted on the rising edge of SCK starting with the most significant bit. CE#
must be driven low before an instruction is entered and must be driven high after the last bit of the
instruction has been shifted in (except for Read, Read-ID, and Read-Status-Register instructions). Any
low-to-high transition on CE#, before receiving the last bit of an instruction bus cycle, will terminate the
instruction in progress and return the device to standby mode. Instruction commands (Op Code),
addresses, and data are all input from the most significant bit (MSB) first.
Table 6: Device Operation Instructions for SST25WF080
Instruction Description
Op Code Cycle1
Address Dummy Data Maximum
Cycle(s)2 Cycle(s) Cycle(s) Frequency
Read
Read Memory
0000 0011b (03H)
3
0 1 to ∞ 33 MHz
High-Speed Read Memory at Higher Speed 0000 1011b (0BH)
Read
3
1 1 to ∞
4 KByte Sec- Erase 4 KByte of memory array 0010 0000b (20H)
tor-Erase3
3
00
32 KByte
Erase 32 KByte block
Block-Erase4 of memory array
0101 0010b (52H)
3
00
64 KByte
Erase 64 KByte block
Block-Erase5 of memory array
1101 1000b (D8H)
3
00
Chip-Erase Erase Full Memory Array
0110 0000b (60H) or
1100 0111b (C7H)
0
00
Byte-Program To Program One Data Byte
0000 0010b (02H)
3
01
AAI-Word-
Program6
RDSR7
EWSR8
Auto Address Increment
Programming
Read-Status-Register
Enable-Write-Status-Register
1010 1101b (ADH)
0000 0101b (05H)
0110 0000b (50H)
3
0
0
0 2 to ∞
75 MHz
0 1 to ∞
00
WRSR
WREN8
Write-Status-Register
Write-Enable
0000 0001b (01H)
0000 0110b (06H)
0
0
01
00
WRDI
Write-Disable
0000 0100b (04H)
0
00
RDID9
Read-ID
1001 0000b (90H) or
1010 1011b (ABH)
3
0 1 to ∞
EBSY
Enable SO to output RY/BY# 0111 0000b (70H)
status during AAI programming
0
00
DBSY
Disable SO to output RY/BY# 1000 0000b (80H)
status during AAI programming
0
00
JEDEC-ID JEDEC ID read
1001 1111b (9FH)
0
0 3 to ∞
EHLD
Enable HOLD# pin functionality 1010 1010b (AAH)
of the RST#/HOLD# pin
0
00
T6.0 25024
1. One bus cycle is eight clock periods.
2. Address bits above the most significant bit of each density can be VIL or VIH.
3. 4 KByte Sector-Erase addresses: use AMS-A12, remaining addresses are don’t care but must be set either at VIL or VIH.
4. 32 KByte Block-Erase addresses: use AMS-A15, remaining addresses are don’t care but must be set either at VIL or VIH.
©2012 Silicon Storage Technology, Inc.
11
DS25024C
10/12
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet SST25WF080.PDF ] | |
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