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SST39VF401C 데이터시트 PDF




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부품번호 SST39VF401C 기능
기능 4 Mbit (x16) Multi-Purpose Flash Plus
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SST39VF401C 데이터시트, 핀배열, 회로
4 Mbit (x16) Multi-Purpose Flash Plus
SST39VF401C / SST39VF402C / SST39LF401C / SST39LF402C
Data Sheet
SST39VF401C / SST39VF402C / SST39LF401C / SST39LF402C are 256K x16
CMOS Multi-Purpose Flash Plus (MPF+) manufactured with proprietary, high per-
formance CMOS SuperFlash® technology. The split-gate cell design and thick-
oxide tunneling injector attain better reliability and manufacturability compared
with alternate approaches. SST39LF401C/402C write (Program or Erase) with a
3.0-3.6V power supply. SST39VF401C/402C write with a 2.7-3.6V power supply.
These devices conforms to JEDEC standard pinouts for x16 memories.
Features
• Organized as 256K x16
• Single Voltage Read and Write Operations
– 2.7-3.6V for SST39VF401C/402C
– 3.0-3.6V for SST39LF401C/402C
• Superior Reliability
– Endurance: 100,000 Cycles (Typical)
– Greater than 100 years Data Retention
• Low Power Consumption (typical values at 5 MHz)
– Active Current: 5 mA (typical)
– Standby Current: 3 µA (typical)
– Auto Low Power Mode: 3 µA (typical)
• Hardware Block-Protection/WP# Input Pin
– Top Block-Protection (top 8 KWord)
– Bottom Block-Protection (bottom 8 KWord)
• Sector-Erase Capability
– Uniform 2 KWord sectors
• Block-Erase Capability
– Flexible block architecture; one 8-, two 4-, one 16-, and
seven 32-KWord blocks
• Chip-Erase Capability
• Erase-Suspend/Erase-Resume Capabilities
• Hardware Reset Pin (RST#)
• Latched Address and Data
• Security-ID Feature
– 128 bits; User: 128 words
• Fast Read Access Time:
– 70 ns for SST39VF401C/402C
– 55 ns for SST39LF401C/402C
• Fast Erase and Word-Program:
– Sector-Erase Time: 18 ms (typical)
– Block-Erase Time: 18 ms (typical)
– Chip-Erase Time: 40 ms (typical)
– Word-Program Time: 7 µs (typical)
• Automatic Write Timing
– Internal VPP Generation
• End-of-Write Detection
– Toggle Bits
– Data# Polling
– Ready/Busy# Pin
• CMOS I/O Compatibility
• JEDEC Standard
– Flash EEPROM Pinouts and command sets
• Packages Available
– 48-lead TSOP (12mm x 20mm)
– 48-ball TFBGA (6mm x 8mm)
– 48-ball WFBGA (4mm x 6mm)
• All devices are RoHS compliant
©2014 Silicon Storage Technology, Inc.
www.microchip.com
DS20005053B
04/14




SST39VF401C pdf, 반도체, 판매, 대치품
4 Mbit (x16) Multi-Purpose Flash Plus
SST39VF401C / SST39VF402C / SST39LF401C / SST39LF402C
Pin Assignment
Data Sheet
A15
A14
A13
A12
A11
A10
A9
A8
NC
NC
WE#
RST#
NC
WP#
RY/BY#
NC
A17
A7
A6
A5
A4
A3
A2
A1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
Standard Pinout
Top View
Die Up
Figure 2: Pin Assignments for 48-Lead TSOP
48 A16
47 NC
46 VSS
45 DQ15
44 DQ7
43 DQ14
42 DQ6
41 DQ13
40 DQ5
39 DQ12
38 DQ4
37 VDD
36 DQ11
35 DQ3
34 DQ10
33 DQ2
32 DQ9
31 DQ1
30 DQ8
29 DQ0
28 OE#
27 VSS
26 CE#
25 A0
1434 48-tsop EK P1.0
TOP VIEW (balls facing down)
6
A13 A12 A14 A15 A16 NC DQ15 VSS
5
A9 A8 A10 A11 DQ7 DQ14 DQ13 DQ6
4
WE# RST# NC NC DQ5 DQ12 VDD DQ4
3
RY/BY#WP# NC NC DQ2 DQ10 DQ11 DQ3
2
A7 A17 A6 A5 DQ0 DQ8 DQ9 DQ1
1
A3 A4 A2 A1 A0 CE# OE# VSS
ABCDEFGH
25053 48-tfbga B3K P2.0
Figure 3: Pin Assignments for 48-Ball TFBGA
©2014 Silicon Storage Technology, Inc.
4
DS20005053B
04/14

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SST39VF401C 전자부품, 판매, 대치품
4 Mbit (x16) Multi-Purpose Flash Plus
SST39VF401C / SST39VF402C / SST39LF401C / SST39LF402C
Device Operation
Data Sheet
Commands are used to initiate the memory operation functions of the device. Commands are written
to the device using standard microprocessor write sequences. A command is written by asserting WE#
low while keeping CE# low. The address bus is latched on the falling edge of WE# or CE#, whichever
occurs last. The data bus is latched on the rising edge of WE# or CE#, whichever occurs first.
The SST39VF401C/402C and SST39LF401C/402C also have the Auto Low Power mode which puts
the device in a near standby mode after data has been accessed with a valid Read operation. This
reduces the IDD active read current from typically 5 mA to typically 3 µA. The Auto Low Power mode
reduces the typical IDD active read current to the range of 2 mA/MHz of Read cycle time. The device
exits the Auto Low Power mode with any address transition or control signal transition used to initiate
another Read cycle, with no access time penalty. Note that the device does not enter Auto-Low Power
mode after power-up with CE# held steadily low, until the first address transition or CE# is driven high.
Read
The Read operation of the SST39VF401C/402C and SST39LF401C/402C is controlled by CE# and OE#,
both have to be low for the system to obtain data from the outputs. CE# is used for device selection.
When CE# is high, the chip is deselected and only standby power is consumed. OE# is the output con-
trol and is used to gate data from the output pins. The data bus is in high impedance state when either
CE# or OE# is high. Refer to the Read cycle timing diagram for further details (Figure 6).
Word-Program Operation
The SST39VF401C/402C and SST39LF401C/402C are programmed on a word-by-word basis. Before
programming, the sector where the word exists must be fully erased. The Program operation is accom-
plished in three steps. The first step is the three-byte load sequence for Software Data Protection. The
second step is to load word address and word data. During the Word-Program operation, the
addresses are latched on the falling edge of either CE# or WE#, whichever occurs last. The data is
latched on the rising edge of either CE# or WE#, whichever occurs first. The third step is the internal
Program operation which is initiated after the rising edge of the fourth WE# or CE#, whichever occurs
first. The Program operation, once initiated, will be completed within 10 µs. See Figures 7 and 8 for
WE# and CE# controlled Program operation timing diagrams and Figure 22 for flowcharts. During the
Program operation, the only valid reads are Data# Polling and Toggle Bit. During the internal Program
operation, the host is free to perform additional tasks. Any commands issued during the internal Pro-
gram operation are ignored. During the command sequence, WP# should be statically held high or low.
Sector/Block-Erase Operation
The Sector- (or Block-) Erase operation allows the system to erase the device on a sector-by-sector (or
block-by-block) basis. The SST39VF401C/402C and SST39LF401C/402C offer both Sector-Erase and
Block-Erase mode.
The sector architecture is based on a uniform sector size of 2 KWord. The Block-Erase mode is based
on non-uniform block sizes—seven 32 KWord, one 16 KWord, two 4 KWord, and one 8 KWord blocks.
See Figure 2 for top and bottom boot device block addresses. The Sector-Erase operation is initiated
by executing a six-byte command sequence with Sector-Erase command (50H) and sector address
(SA) in the last bus cycle. The Block-Erase operation is initiated by executing a six-byte command
sequence with Block-Erase command (30H) and block address (BA) in the last bus cycle. The sector
or block address is latched on the falling edge of the sixth WE# pulse, while the command (30H or
50H) is latched on the rising edge of the sixth WE# pulse. The internal Erase operation begins after the
©2014 Silicon Storage Technology, Inc.
7
DS20005053B
04/14

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부품번호상세설명 및 기능제조사
SST39VF401C

4 Mbit (x16) Multi-Purpose Flash Plus

Microchip
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