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PDF SST39LF401C Data sheet ( Hoja de datos )
| Número de pieza | SST39LF401C | |
| Descripción | 4 Mbit (x16) Multi-Purpose Flash Plus | |
| Fabricantes | Microchip | |
| Logotipo |  |
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4 Mbit (x16) Multi-Purpose Flash Plus
SST39VF401C / SST39VF402C / SST39LF401C / SST39LF402C
Data Sheet
SST39VF401C / SST39VF402C / SST39LF401C / SST39LF402C are 256K x16
CMOS Multi-Purpose Flash Plus (MPF+) manufactured with proprietary, high per-
formance CMOS SuperFlash® technology. The split-gate cell design and thick-
oxide tunneling injector attain better reliability and manufacturability compared
with alternate approaches. SST39LF401C/402C write (Program or Erase) with a
3.0-3.6V power supply. SST39VF401C/402C write with a 2.7-3.6V power supply.
These devices conforms to JEDEC standard pinouts for x16 memories.
Features
• Organized as 256K x16
• Single Voltage Read and Write Operations
– 2.7-3.6V for SST39VF401C/402C
– 3.0-3.6V for SST39LF401C/402C
• Superior Reliability
– Endurance: 100,000 Cycles (Typical)
– Greater than 100 years Data Retention
• Low Power Consumption (typical values at 5 MHz)
– Active Current: 5 mA (typical)
– Standby Current: 3 µA (typical)
– Auto Low Power Mode: 3 µA (typical)
• Hardware Block-Protection/WP# Input Pin
– Top Block-Protection (top 8 KWord)
– Bottom Block-Protection (bottom 8 KWord)
• Sector-Erase Capability
– Uniform 2 KWord sectors
• Block-Erase Capability
– Flexible block architecture; one 8-, two 4-, one 16-, and
seven 32-KWord blocks
• Chip-Erase Capability
• Erase-Suspend/Erase-Resume Capabilities
• Hardware Reset Pin (RST#)
• Latched Address and Data
• Security-ID Feature
– 128 bits; User: 128 words
• Fast Read Access Time:
– 70 ns for SST39VF401C/402C
– 55 ns for SST39LF401C/402C
• Fast Erase and Word-Program:
– Sector-Erase Time: 18 ms (typical)
– Block-Erase Time: 18 ms (typical)
– Chip-Erase Time: 40 ms (typical)
– Word-Program Time: 7 µs (typical)
• Automatic Write Timing
– Internal VPP Generation
• End-of-Write Detection
– Toggle Bits
– Data# Polling
– Ready/Busy# Pin
• CMOS I/O Compatibility
• JEDEC Standard
– Flash EEPROM Pinouts and command sets
• Packages Available
– 48-lead TSOP (12mm x 20mm)
– 48-ball TFBGA (6mm x 8mm)
– 48-ball WFBGA (4mm x 6mm)
• All devices are RoHS compliant
©2014 Silicon Storage Technology, Inc.
www.microchip.com
DS20005053B
04/14
1 page  
4 Mbit (x16) Multi-Purpose Flash Plus
SST39VF401C / SST39VF402C / SST39LF401C / SST39LF402C
Data Sheet
TOP VIEW (balls facing down)
6
A2 A4 A6 A17 NC NC WE# RST# A9 A11
5
A1 A3 A7 WP#
4
RY/BY# A10 A13 A14
A0 A5 NC
3
A8 A12 A15
CE# DQ8 DQ10
2
DQ4 DQ11 A16
1 VSS OE# DQ9 NC
NC DQ5 DQ6 DQ7
DQ0 DQ1 DQ2 DQ3 VDD DQ12 DQ13 DQ14 DQ15 VSS
AB C D E F G H J K L
25053 48-wfbga MAQ P3.0
Figure 4: Pin Assignments for 48-Ball WFBGA
Table 1: Pin Description
Symbol Pin Name
Functions
AMS1-A0
DQ15-DQ0
Address Inputs To provide memory addresses.
During Sector-Erase AMS-A11 address lines will select the sector.
During Block-Erase AMS-A15 address lines will select the block.
Data Input/output To output data during Read cycles and receive input data during Write cycles.
Data is internally latched during a Write cycle.
The outputs are in tri-state when OE# or CE# is high.
WP#
Write Protect
To protect the top/bottom boot block from Erase/Program operation when
grounded.
RST#
Reset
To reset and return the device to Read mode.
CE#
Chip Enable
To activate the device when CE# is low.
OE#
Output Enable To gate the data output buffers.
WE#
Write Enable
To control the Write operations.
VDD Power Supply To provide power supply voltage: 2.7-3.6V for SST39VF401C/402C or 3.0-3.6V
for SST39LF401C/402C
VSS Ground
NC No Connection Unconnected pins.
RY/BY#
Ready/Busy#
To output the status of a Program or Erase operation
RY/BY# is a open drain output, so a 10K - 100K pull-up resistor is required
to allow RY/BY# to transition high indicating the device is ready to read.
1. AMS = Most significant address
AMS = A17
T1.2 25053
©2014 Silicon Storage Technology, Inc.
5
DS20005053B
04/14
5 Page 
4 Mbit (x16) Multi-Purpose Flash Plus
SST39VF401C / SST39VF402C / SST39LF401C / SST39LF402C
Data Sheet
the specific software command codes. During SDP command sequence, invalid commands will abort
the device to read mode within TRC. The contents of DQ15-DQ8 can be VIL or VIH, but no other value,
during any SDP command sequence.
Common Flash Memory Interface (CFI)
The SST39VF401C/402C and SST39LF401C/402C also contain the CFI information to describe the
characteristics of the device. In order to enter the CFI Query mode, the system writes a three-byte
sequence, same as product ID entry command with 98H (CFI Query command) to address 555H in
the last byte sequence. Additionally, the system can use the one-byte sequence with 55H on the
Address and 89H on the Data Bus to enter the CFI Query mode. Once the device enters the CFI
Query mode, the system can read CFI data at the addresses given in Tables 8 through 10. The system
must write the CFI Exit command to return to Read mode from the CFI Query mode.
Product Identification
The Product Identification mode identifies the devices as the SST39VF401C / SST39VF402C /
SST39LF401C / SST39LF402C, and manufacturer as Microchip. This mode may be accessed soft-
ware operations. Users may use the Software Product Identification operation to identify the part (i.e.,
using the device ID) when using multiple manufacturers in the same socket. For details, see Table 7 for
software operation, Figure 14 for the Software ID Entry and Read timing diagram and Figure 24 for the
Software ID Entry command sequence flowchart.
Table 5: Product Identification
Manufacturer’s ID
Device ID
SST39VF401C/SST39LF401C
SST39VF402C/SST39LF402C
Address
0000H
0001H
0001H
Data
BFH
2321H
2322H
T5.2 25053
Product Identification Mode Exit/CFI Mode Exit
In order to return to the standard Read mode, the Software Product Identification mode must be exited.
Exit is accomplished by issuing the Software ID Exit command sequence, which returns the device to
the Read mode. This command may also be used to reset the device to the Read mode after any inad-
vertent transient condition that apparently causes the device to behave abnormally, e.g., not read cor-
rectly. Please note that the Software ID Exit/CFI Exit command is ignored during an internal Program
or Erase operation. See Table 7 for software command codes, Figure 16 for timing waveform, and Fig-
ure 25 for flowcharts.
©2014 Silicon Storage Technology, Inc.
11
DS20005053B
04/14
11 Page | ||
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