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기능 IO-Link compliant HV Line Driver IC
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ZIOL2202 데이터시트, 핀배열, 회로
Data Sheet
Rev. 2.2.1 / January 2012
ZIOL2xxx IC Family
IO-Link compliant HV Line Driver IC Family
Data Sheet
January 31, 2012
© 2012 Zentrum Mikroelektronik Dresden AG — Rev. 2.2.1
All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without
the prior written consent of the copyright owner. The information furnished in this publication is PRELIMINARY and subject to
changes without notice.
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ZIOL2202 pdf, 반도체, 판매, 대치품
ZIOL2xxx – IC Family
IO-Link compliant HV Line Driver IC Family
List of Figures
Figure 2.1 Max. Total Power Dissipation ................................................................................................................7
Figure 2.2 Efficiency of the DC/DC converter for VOUT=5V, C=10µF and L=10µH ............................................14
Figure 3.1 Functional Block Diagram of the ZIOL2xxx .........................................................................................15
Figure 3.2 ZIOL24xx Transceiver Data Path in Principle......................................................................................16
Figure 3.3 ZIOL22xx Transceiver Data Path in Principle......................................................................................17
Figure 3.4 ZIOL21xx Transceiver Data Path in Principle......................................................................................18
Figure 3.5 ZIOL24xx in Device and Master Mode Application..............................................................................21
Figure 3.6 Typical IO-Link Device Configuration with HS driver only ...................................................................24
Figure 3.7 Wake-Up Signal Recognition...............................................................................................................26
Figure 3.8 The Basic Scheme of the IC Self Protection .......................................................................................28
Figure 3.9 Memory Unit.........................................................................................................................................30
Figure 3.10 General timing of a byte transfer .........................................................................................................32
Figure 3.11 Structure of SPI accesses ...................................................................................................................33
Figure 3.12 SPI Command Structure......................................................................................................................34
Figure 3.13 SPI Timing ...........................................................................................................................................36
Figure 3.14 Interrupt (INT_L pin) and Wake-up (WURQ_L pin) Signaling .............................................................47
Figure 3.15 COM Channel Lock Control.................................................................................................................49
Figure 3.16 AUX Channel Lock Control..................................................................................................................50
Figure 3.17 Over-Temperature Lock Control ..........................................................................................................51
Figure 3.18 Internal IC Sensors and related Overload and Over-Temperature Detection Circuits ........................53
Figure 3.19 Low Voltage Supply Concept...............................................................................................................55
Figure 3.20 PFD Working Principle.........................................................................................................................56
Figure 3.21 DC/DC Converter in Principle ..............................................................................................................58
Figure 3.22 DC/DC Converter Output Voltage as Function of R1 (R2 = 10kOhms) ..............................................60
Figure 3.23 High frequency critical loops of DC/DC converter for PCB layout.......................................................61
Figure 3.24 PCB layout of Evaluation board as an example ..................................................................................62
Figure 4.1 Simplified Application Circuit with the ZIOL2xxx in Device Mode .......................................................63
Figure 4.2 Simplified Application Circuit with the ZIOL2xxx in Master Mode .......................................................64
Figure 4.3 Power Line Fail Detection....................................................................................................................65
Figure 4.4 PCB Layout Recommendations...........................................................................................................66
Figure 6.1 Pin Diagram of the ZIOL2xxx...............................................................................................................71
Figure 6.2 Package Dimensions ...........................................................................................................................72
Figure 6.3 Top Marking of the ZIOL2xxx ..............................................................................................................73
Figure 9.1 Register Representation in Principle (Example)..................................................................................77
Figure 10.1 Peak Register Access Scenarios.........................................................................................................81
Figure 10.2 Overload Counter Behavior in permanent Over-Current Situations ....................................................82
Figure 10.3 Overload Counter Behavior in permanent Over-Temperature Situations ...........................................83
Figure 10.4 Overload Counter Behavior in typical Over-Temperature Situations ..................................................84
Figure 10.5 Partial Reset of Overload Counter or the entire Lock circuit ...............................................................85
Data Sheet
January 31, 2012
© 2012 Zentrum Mikroelektronik Dresden AG — Rev. 2.2.1
All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without
the prior written consent of the copyright owner. The information furnished in this publication is PRELIMINARY and subject to
changes without notice.
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ZIOL2202 전자부품, 판매, 대치품
ZIOL2xxx – IC Family
IO-Link compliant HV Line Driver IC Family
2 Electrical Characteristics
2.1. Absolute Maximum Ratings
Parameters apply in operation temperature range and without time limitations.
Table 2.1 Absolute Maximum Ratings
Symbol Parameter
VDD_HV
VHV
VLV
Vimp
VESD
Supply voltage
Voltage at HV pins
Voltage at LV pins
Impulse voltage withstand
Abs. ESD test voltage
Ts Junction temperature
Ta Storage temperature
Ptot Average total power dissipation
1) Average die-temperature.
2) Exceptions are the digital input pins (µC
interface) which tolerate 5V logic signals (refer
to Table 5.1).
3) The allowed total power dissipation depends
on the in the PCB design achieved thermal
resistance Rth (package/ambient) and the
ambient operation temperature as shown in
Figure 2.1. In order to obtain optimal heat
distribution (Rth < 35K/W) certain PCB layout
rules shall be applied. Those rules are
described in the application note for the used
QFN package (refer to chapter 8, [4]).
Min Max Unit Conditions
-0.3 40 V
-0.3 VDD_HV+0.3 V
-0.3 VDD_LV+0.3 V
2)
60 V according to IEC 60947-5-2
2k V according to HBM
125 °C 1)
-50 150 °C
2.6 W integration period < 10ms 3)
Figure 2.1 Max. Total Power Dissipation
3
2,5 Rth = 35K/W
2
1,5
Rth = 45K/W
1
0,5
0
-40 -20 0 20 40 60 80
Tamb/°C
Data Sheet
January 31, 2012
© 2012 Zentrum Mikroelektronik Dresden AG — Rev. 2.2.1
All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without
the prior written consent of the copyright owner. The information furnished in this publication is PRELIMINARY and subject to
changes without notice.
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