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PDF NT6861 Data sheet ( Hoja de datos )
| Número de pieza | NT6861 | |
| Descripción | 8-Bit Microcontroller | |
| Fabricantes | Novatek | |
| Logotipo |  |
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NT6861
Features
n 40 pin DIP & 42 pin SDIP package
n Operating Voltage Range: 4.5V to 5.5V
n CMOS technology for low power consumption
n Crystal oscillator or ceramic resonator* available
n 6502 8-bit CMOS CPU core
n 8MHz operation of frequency
n 4/8/12/16/24K bytes ROM are available
n 256 bytes of RAM (which stores EDID for DDC1/2B)
n One 8-bit pre-loadable base timer
n 14 channels of 8 bit PWM outputs:
6 channel with 5V open drain and 8 channel with 12V
open drain
n 2 channel A/D converters with 6-bit resolution
General Description
NT6861 is a monitor component µC for auto-sync and
digital controlled applications. It contains a 6502
8-bit CPU core, 256 bytes of RAM used as working RAM
and stack area, 24K bytes of ROM maximum for
programming, 14-channel 8-bit PWM D/A converters, 2-
channel A/D converters for key detection saving I/O pins,
one 8 bit pre-loadable base timer, internal Hsync and
Vsync signals processor providing mode detection,
watch-dog timer preventing system from abnormal
operation, and an I2C bus interface.
8-Bit Microcontroller for Monitor
n 24 bi-directional I/O port pins and 1 I/P pin
n Hsync/Vsync signal processor
n Hardware sync signals polarity & freq. evaluator
n Built-In I2C bus interface
n Supporting VESA DDC1/2B function
n Six-interrupt sources
- INTV (Vsync INT)
- INTE (External INT with rising edge trigger)
- INTMR (Timer INT )
- INTA (Slave Address Matched INT)
- INTD (Shift Register INT)
- INTS (SCL GO-LOW INT)
n Hardware watch-dog timer function
Users can store EDID data in the 128 bytes of RAM for
DDC1/2B, so that users can save the cost of dedicated
EEPROM for EDID. Half frequency output function can
save external one-shot circuit. All of these designs create
savings in component costs.
* The frequency deviation of ceramic resonator has
+/- 6% maximum.
1 V2.0
1 page  
NT6861
Functional Descriptions
1. 6502 CPU
The 6502 is an 8-bit CPU that provides 56 instructions, decimal and binary arithmetic, thirteen addressing modes, true indexing
capability, programmable stack pointer with variable length stack, a wide selection of addressable memory, and interrupt input
options.
The CPU clock cycle is 4MHz (8MHz system clock divided by 2). Refer to 6502 data sheet for more details.
7
Accumulator A
0
7
Index Register Y
0
7
Index Register X
0
15
Program Counter PCH
PCL
8
7
7
Stack Pointer SP
0
0
7
NV
0
B D I Z C Status Register P
Carry
Zero
IRQ Disable
Decimal Mode
BRK Command
Overflow
Negative
1 = TRUE
1 = Result ZERO
1 = DISABLE
1 = TRUE
1 = BRK
1 = TRUE
1 = NEG
Figure 1. 6502 CPU Registers and Status Flags
5
5 Page 
NT6861
5. Timing Generator
This block generates the system timing and control signal to be supplied to the CPU and on-chip peripherals. A crystal quartz,
ceramic resonator, or an external clock signal provided to the OSCI pin generates 8MHz system clock,
(4 MHz for CPU), Although internal circuits have a feedback resistor and compacitor included, components may be externally
added to ensure proper operation. The typical clock frequency is 8MHz. This frequency will affect the operation of on-chip
peripherals whose operating frequency is based on the system clock .
8MHz
OSCI
External Clock
OSCO
Unconnected
(1)
NT6861
Figure 2. Oscillator Connections
OSCI
OSCO
NT6861
(2)
6. A/D Converter
The analog to digital converter is a single 6-bit successive approximation converter. Analog voltage is supplied from external
sources to the A/D input pins and the results of the conversion are stored in the 6-bit data latch registers
($000D & $000E). The A/D converter is controlled by the control bits in the A/D control register ENDAC. Refer to the A/D
channel format table A/D input pins activation. A conversion is started by setting a '0' to the CONVERSION START bit ( CSTA )
in the A/D control register ($000D). This automatically sets the CONVERSION END bit ( CEND ) to '1'. When a conversion has
been finished, CEND bit automatically clears to '0'. The A/D conversion data in the AD LATCH registers ($000D & $000E) is
valid digital data.
The analog voltage to be measured should be stabled during the conversion operation. The variation should exceed
1/2 LSB for accuracy in measurement. Please refer Figure 3 for checking the linearity of A/D.
A/D Channel Format Table
ENAD1
0
0
1
1
ENAD0
0
1
0
1
P11 line
AD1
AD1
P11
P11
P10 line
AD0
P10
AD0
P10
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet NT6861.PDF ] | |
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