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NT6868A 데이터시트 PDF




Novatek에서 제조한 전자 부품 NT6868A은 전자 산업 및 응용 분야에서
광범위하게 사용되는 반도체 소자입니다.


PDF 형식의 NT6868A 자료 제공

부품번호 NT6868A 기능
기능 Keyboard Controller
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NT6868A 데이터시트, 핀배열, 회로
NT6868A
Keyboard Controller
Features
n Built-in 6502 8-bit CPU
n 2 MHz CPU operation frequency
n 4K bytes of ROM
n 128 bytes of SRAM
n One 8-bit programmable base timer with
1 - 256 µsec interval
n 29 programmable bi-directional I/O pins
n 3 LED direct sink pins with internal serial resistors
n Mask optional for built-in RC oscillator with an
external resistor or external ceramic resonator applied
n Watch-dog timer
n Built-in power-on reset
n Built-in low voltage reset
n CMOS technology for low power consumption
n Available in 40 pin DIP package and 40 pad CHIP
FORM
General Description
NT6868A is a single chip micro-controller for keyboard
applications. It incorporates a 6502 8-bit CPU core, 4K
bytes of ROM, and 128 bytes of RAM used as working
RAM and stack area. It also includes 29 programmable
bi-directional I/O pins and one 8-bit pre-loadable base
timer. Additionally, it includes a built-in low voltage
reset, a 4MHz RC oscillator that requires only a resistor
externally applied or a 4MHz ceramic resonator, and a
watch-dog timer that prevents system standstill.
Pin Configuration
Pad Configuration
GND
NC
DATA
CLK
P30
P31
P32
P33
P34
RESET
P00
P01
P02
P03
P04
P05
P06
P07
P10
P11
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40 OSCI
39 R/OSCO
38 VDD
37 LED2
36 LED1
35 LED0
34 P27
33 P26
32 P25
31 P24
30 P23
29 P22
28 P21
27 P20
26 P17
25 P16
24 P15
23 P14
22 P13
21 P12
PPPPPPPPPP
1111111100
7654321076
26 25 24 23 22 21 20 19 18 17
16 P05
15 P04
P20 27
14 P03
P21 28
13 P02
P22 29
12 P01
P23 30
P24 31
NT6868AH
11 P00
10 RESET
P25 32
9 P34
P26 33
8 P33
P27 34
7 P32
LED0
LED1
35
36
37 38 39 40 1
2345
6 P31
L V R OG
E D / SN
D DO CD
2 SI
C
O
NDCP
CAL 3
TK0
A
1 V2.1




NT6868A pdf, 반도체, 판매, 대치품
NT6868A
System Reserved Registers
Address
$00C0
$00C1
Register
BT
TCON
$00C2
$00C3
$00C4
$00C5
$00C6
$00C7
$00C8
$00C9
$00CA
$00CB
$00CC
$00CD
$00CE
$00CF
CLRIRQX
PORT0
PORT1
PORT2
PORT3
CLK
DATA
LED
CLRWDT
X
X
X
X
X
Bit7
BT7
-
-
PD07
PD17
PD27
-
-
-
-
0
X
X
X
X
X
Bit6
BT6
-
-
PD06
PD16
PD26
-
-
-
-
1
X
X
X
X
X
Bit5
BT5
-
-
PD05
PD15
PD25
-
-
-
-
0
X
X
X
X
X
Bit4
BT4
-
-
PD04
PD14
PD24
PD34
-
-
-
1
X
X
X
X
X
Bit3
BT3
-
-
PD03
PD13
PD23
PD33
-
-
-
0
X
X
X
X
X
Bit2
BT2
-
-
PD02
PD12
PD22
PD32
-
-
LED2
1
X
X
X
X
X
Bit1
BT1
-
-
PD01
PD11
PD21
PD31
-
-
LED1
0
X
X
X
X
X
Bit0
BT0
ENBT
CLRIRQTMR
PD00
PD10
PD20
PD30
CLK
DATA
LED0
1
X
X
X
X
X
W
W
W
RW
RW
RW
RW
RW
RW
W
W
X
X
X
X
X
- : no effect
X : access not allowed
4K X 8 ROM
Power-On Reset
The built-in ROM program code, executed by the 6502
CPU, has a capacity of 4K X 8 bits and is addressed
from F000H to FFFFH.
128 X 8 SRAM
Built-in power-on reset circuit can generate a 150ms
pulse to reset the entire chip. The beginning of the
150ms pulse occurs at 60% of VDD when powered on.
The built-in SRAM is used for general purpose data
memory and for the stack area. SRAM is addressed from
0000H to 007FH. User can allocate stack area in the
SRAM by setting stack pointer register (S). Because the
6502C default stack pointer is 01FFH, it must be
mapped to 007FH. Mapping from 01XX to 00XX is done
internally by setting the S register to 7FH via software
programming.
For example :
power
VDD
60%
The start of 150ms pulse
t
LDX #$7F
TXS
4

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NT6868A 전자부품, 판매, 대치품
NT6868A
LED Port
There are 3 LED direct sink pins which require no external serial resistors. The address is mapped to address $00C9.
Addr.
Bit
7
6
5
4
3
2
1
0
$00C9
LED
-
-
-
-
- LED2 LED1 LED0 (W)
WREN
DB
RST
L
Q
D SD
LED [ 0 ]
WREN
DB
RST
L
Q
D SD
VDD
LED [ 1:2 ]
LED0 Port Structure
LED1, LED2 Port Structures
Watch-Dog Timer
NT6868A implements a watch-dog timer, which protects programs against system standstill. The clock of the watch-dog
timer is derived from the on-chip RC oscillator. The watch-dog timer interval is about 0.175 of a second. The timer must be
cleared within every 0.175 second during normal operation; otherwise, it will overflow and cause a system reset. The
watch-dog timer is cleared and enabled after a system reset. It cannot be disabled by software. The user can clear the
watch-dog timer by writing #55H to CLRWDT ($00CAH) register.
For example:
LDA
STA
#$55
$00CA
Addr.
Bit
7
6
5
4
3
2
1
0
$00CA CLRWDT
0
1
0
1
0
1
0
1 (W)
Low Voltage Reset (LVR) Circuit
The NT6868A will check on the voltage level of power supply. When the voltage level of power supply is below a threshold
of 3.0V (Typical), the LVRC will issue a reset output to the chip until the power voltage level is above the threshold voltage
of 3.0V (Typical) again. As soon as the power voltage arises to 3.0V (Typical), the entire chip will be reset for about
150ms.
RESET
NT6868A can also be externally reset via RESET pin. A reset is initiated when the signal at the RESET pin is held Low
for at least 10 system clock. As soon as RESET signal goes high, the NT6868A begins to be reset for about 150ms. The
following shows the definition of RESET input low pulse width.
V DD
VDD
20%V DD
Trstb
20%V DD
7

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