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PDF TMM41257P-12 Data sheet ( Hoja de datos )
| Número de pieza | TMM41257P-12 | |
| Descripción | N-channel dynamic RAM | |
| Fabricantes | Toshiba | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de TMM41257P-12 (archivo pdf) en la parte inferior de esta página. Total 17 Páginas | ||
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TOSHIBA MOS MEMORY PRODUCT
262,144 WORD X 1 BIT DYNAMIC RAM
SILICON MONOLITHIC
N-CHANNEL SILICON GATE MOS
TMM41257P/T-12
TMM41257P/T-15
DESCRIPTION
The TMM41257P/T is the N-channel dynamic RAM organized 262,144 words by 1 bit. Multiplexed address inputs
permit the TMM41257P/T to be packaged in a standard 16 pin plastic DIP and 18 pin plastic leaded chip carrier. The
package size provides high system bit densities and is compatible with widely available automated testing and insertion
equipment. The double layered MOS technology with polycide and poly Si permits the TMM41257P/T high speed
operation. Also, the advanced circuit techniques have realized low power dissipation. System oriented features include
single power supply of 5V±10% tolerance, direct interfacing capability with high performance logic families such as
schottky TTl. In addition to the RAS only refresh mode, a CAS before RAS automatic refresh is available. Another special
feature of TMM41257P/T is nibble mode, allowing the user to serially access 4 bits of data at a high data rate.
FEATURES
• 262,144 words by 1 bit organization
• Fast access time and cycle time
RAS Access Time
CAS Access Time
Cycle Time
Nibble Mode
Access Time
Nibble Mode
Cycle Time
TMM41257P/T-12 TMM41257P/T-15
-1--------
120ns
150ns
60ns ---_.
220ns
75ns
260ns
30ns
40ns
55ns
70ns
• Single power supply of 5V±10% with a built-in
VBB generator
• Low Power:
385mW MAX. Operating (TMM41257P/T-12)
330mW MAX. Operating (TMM41257P/T-15)
28mW MAX. Standby
• Output unlatched at cycle end allows two-
dimensional chip selection
• Common I/O capability using "EARLY WRITE"
operation
• Read-Modify-Write, CAS before RAS refresh, RAS-
only refresh, Hidden refresh, and Nibble Mode
capability
• All inputs and output TIL compatible
• 256 refresh cycles/4ms
G Package
Plastic DIP
:TMM41257P
Plastic Leaded Chip Carrier
:TMM41257T
PIN CONNECTION (TOP VIEW)
• Plastic LCC
• Plastic DIP
CAS
VSS
A8 1
DIN 2
I-
:J
O«Z««0<0 0 C') '<t
IwruoI-«z««N
_0:
0:
~
A8
DIN
RAS
AO
A2
A1
VCC
PIN NAMES
AO - A8
CAS
DIN
DOUT
RAS
WRITE
VCC
- - - -------~-
VSS
---
Address Inputs
Column Address Strobe
Data In
Data Out
Row Address Strobe
Read/Write Input
Power (+5V)
----------------.
Ground
----
--
---
---
VSS
CAS
WRITE
A3
A4
A5
A7
AO
A1
A2
A3
A4
A5
A6
A7
A8
BLOCK DIAGRAM
DOUT
MEMORY
ARRAY
- A-33 -
1 page  
TIMING WAVEFORMS
-READ CYCLE
TMM41257P/T-12
TMM41257P/T-15
AD-AS
DOUT
-WRITE CYCLE (EARLY WRITE)
RAS
VIH
VIL
CAS
VIH
VIL
AD-A8
VIH
VIL
WRITE
VIH
VIL
~ Don'ICare
DOUT
----------------------------- OPEN----------- ~ Don'ICare
- A-37 -
5 Page 
• CAS BEFORE RAS REFRESH COUNTER TEST CYCLE
TMM41257P/T-12
TMM41257P/T-15
AO-A8
READ CYCLE
DOUT
[ WRITE
WRITE CYCLE
--------------------------~-----------OPEN
READ-WRITE/READ-MODIFY-WRITE CYCLE
DOUT
- A-43 -
VALID
DATA
~ Don'ICare
11 Page | ||
| Páginas | Total 17 Páginas | |
| PDF Descargar | [ Datasheet TMM41257P-12.PDF ] | |
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