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PDF TMM41257AP-12 Data sheet ( Hoja de datos )
| Número de pieza | TMM41257AP-12 | |
| Descripción | N-channel dynamic RAM | |
| Fabricantes | Toshiba | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de TMM41257AP-12 (archivo pdf) en la parte inferior de esta página. Total 19 Páginas | ||
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TOSHIBA MOS MEMORY PRODUCT
~~L~~~~4~~~~I~H~CBIT DYNAMIC RAM TMM41257 APIATI AZ-l 0, TMM41257 APIATI AZ-12
N-CHANNEL SILICON GAlE CMOS
TMM41257 AP/AT/AZ-15
DESCRIPTION
*This is advanced information and specifications are subject to
change without notice.
The TMM41257AP/AT/AZ is an N-channel dynamic RAM organized 262,144 words by 1 bit. Multiplexed
address inputs permit the TMM41257AP/AT/AZ to be packaged in a standard 16 pin plastic DIP, 18 pin PLCC and
16 pin ZIP. The package size allows for high system bit densities and is compatible with widely available automated
testing and insertion equipment. The double layered MOS technology with polycide and poly Si permits the
TMM41257AP/AT/AZ high speed operation. Also, the advanced circuit techniques have achieved low power
dissipation. System oriented features include single power supply of 5V±10% tolerance, direct interfacing capability
with high performance logic families such as schottky TTL. In addition to the RAS-only refresh mode, a CAS-before-
RAS automatic refresh is available. Another special feature of the TMM4125 7AP/ AT/ AZ is nibble mode which allows
the user to serially access 4 bits of data at a high data rate.
FEATURES
• 262,144 words by 1 bit organization
• Output unlatched at cycle end al-
• Fast access time and cycle time
lows two-dimensional chip selec-
T~lli4l257AP/AT/AZ-lO/-12/-l5
RAS Access Time
lOOns/120ns/150ns
CAS Access Time
50ns/ 60ns/ 75ns
Cycle Time
190ns/220ns/260ns
Nibble Hode Access Time
25ns/ 30ns/ 40ns
Nibble Mode Cycle Time
50nsj 60ns/ 70ns
tion
• Cornmon I/O capability using
"EARLY WRITE" operation
• Read-Modify-Write, CAS before RAS
refresh, RAS-only refresh, Hidden
refresh, and Nibble Mode capabil-
ity
• Single power supply of 5V±lO% with a built-in VBB • All inputs and output TTL com-
generator
patible
• Low Pm..rer:
• 256 refresh cycles/4ms
440mtJ HAX. Operating (TMM4l257AP/AT/AZ-lO)
• Package
396mW MAX. Operating (T~lli4l257AP/AT/AZ-12)
Plastic DIP
TMM4l257AP
358mW MAX. Operating (T~lli4l257AP/AT/AZ-15)
Plastic Leaded
28mH MAX. Standby
Chip Carrier TMM4l257AT
PIN CONNECTION (TOP VIEW)
Plastic ZIP
TMM4l257AZ
· Plastic LCC
• Plastic ZIP Plastic DIP BLOCK DIAGRA~1
f"'
::>
oO'<DQz' «t"'J.
~
AS
Vss A7
AS Vee
DIN 2
A1
""'-iTCri:riTir....l
AS 1
DIN 2
WlUTE 3
ILW 4.
AO S
A2 S
Vss
CAS
14. DOUT
13 AS
12 A3
11 A4.
Al 10 AS
Vee
PIN NAr~ES
AO '\.0 A8
CAS
DIN
DOUT
RAS
~·1RITE
VCC
VSS
Address Inputs
Column Address Strobe
Data In
Data Out
Row Address Strobe
Read/Hrite Input
Power (+5V)
Ground
AO
A1
A2
A3
to,
AS
AS
A7
AS
ARRAY
- A-51 -
1 page  
TMM41257 AP/AT/AZ-l 0, TMM41257 AP/AT/AZ-12
TMM41257AP/AT/AZ-15
NOTES:
1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause
permanent damage to the device.
2. All voltages are referenced to Vss.
3. ICCl, ICC3, ICC4, ICCS depend on cycle rate.
4. ICCl, ICC4 depend on output loading. Specified values are obtained with the
output open.
5. An initial pause of 200~s is required after power-up followed by any 8 RAS
cycles before proper device operation is achieved. In case of using internal
refresh counter, a minimum of 8 CAS Before RAS initialization cycles instead
of 8 RAS cycles are required.
6. AC measurements assume tT=5ns.
7. VIH(min.) and VIL(max.) are reference levels for measuring timing of input
signals. Also, transition times are measured between VIH and VIL.
8. Assumes that tRCD ~ tRCD(max.) • If tRCD is greater than l~:le maximum recommended
value shown in thi~ table, tRAC will increase by the amount that tRCD exceeds
the value shown.
9. Assumes that tRCD 6 tRCD(max.)
10. Measured with a load equivalent to 2 TTL loads and 100pF.
11. tOFF(max.) defines th~ time at which the output achieves the open circuit
condition and is not referenced to output voltage levels.
12. Either tRCH or tRRH must be satisfied for a read cycle.
13. Operation within the tRCD(max.) limit insures that xRAc(max.) can be met.
tRCD(max.) is specified as a reference point only: If tRCD is greater than the
specified tRCD(max.) limit, then access time is controlled exclusively by tCAC.
14. These parameters are referenced to CAS leading edge in early write cycles and
to WRITE leading edge in read-write or read-modify-vrrite cycles.
15. twcs, tcwn and tRWD are not restrictive operating parameters. They are in-
cluded in the data sheet as electrical characteristics only. If twcs ~ t:WCS
(min.), the cycle is an early write cycle and the data out pin will remain
open circuit (high impedance) throughout the entire cycle; If tcwn ~ tcwn(min.)
and tmm ~ tRWD(min.), the cycle is a read-write cycle or read-modify-write cycle
and the data out will contain data read from the selected cell: If neither of
the above sets of conditions is satisfied, the condition of the data out (at
access time) is indeterminate.
- A-55 -
5 Page 
TMM41257 AP/AT/AZ-l 0, TMM41257 AP/AT/AZ-12
TMM41257AP/AT/AZ-15
HIDDEN REFRESH CYCLE (READ)
RAg"
CAS
VIH
VIL
VIH -
VIL -
t ASR
tRCD
tRSH
tCAR
tCAS
tCHR
VIH-
AO-AS
'ROtVIL -
I II
I tRRH
I
7///////TWRITE VIH -
VIL -
~
*@Pff///@ijJjijI7lll4
DOUT
VOF.
VOL
I tRAC
trI - - - - _ - - - -li~'OFF
VALID DATA
~
HIDDEN REFRESH CYCLE (WRITE)
~ Don't care
RAS vIH -
vIL -
CAS VIH
VIL
AO-AS VIH
VIL
WRITE VIH
VIL
VIH
DIN
VIL
DOUT
VOH
VOL
OPEN
~Don't care
- A-61 -
11 Page | ||
| Páginas | Total 19 Páginas | |
| PDF Descargar | [ Datasheet TMM41257AP-12.PDF ] | |
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