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PDF TMM41464P-15 Data sheet ( Hoja de datos )
| Número de pieza | TMM41464P-15 | |
| Descripción | DRAM | |
| Fabricantes | Toshiba | |
| Logotipo |  |
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TOSHIBA MOS MEMORY PRODUCT
65,536 WORD X 4 BIT DYNAMIC RAM
SILICON MONOLITHIC
N-CHANNEL SILICON GATE MOS
TMM41464P-12
TMM41464P-15
DESCRIPTION
The TMM41464P is the new generation dynamic
RAM organized 65,536 word by 4 bit, it is succes-
sor to the industry standard TMM4164AP.
The TMM41464P utilizes TOSHIBA's N-channel/
Silicon gate process technology as well as advanced
circuit techniques to provide wide operating mar-
gins, both internally and to the system user.
Multiplexed address inputs permit the TM M
FEATURES
• 65,536 words by 4 bit organization
• Fast access Time and cycle time
DEVICE
TMM41464P-12
tRAC
120ns
teAe
60ns
tnc
220ns
TMM41464P-15
150ns
75ns
260ns
• Single power supply of 5V± 10% with a built-in
VBB generator
• Low power:
385mW Operating (MAX.) (TMM41464-12)
PIN CONNECTION
VSS
1/04
CAS
1/03
AO
Al
A2
A3
A7
4 1464P to be packaged in a standard 18 pin plastic
DIP. This package size provides high system bit
densities and is compatible with widely available
automated testing and insertion equipment.
System oriented features include single power
supply of 5V± 10% tolerance, direct interfacing
capability with high performance logic families such
as schottky TIL.
330mW Operating (MAX.) (TMM41464-15)
28mW Standby (MAX.)
• Industory standard 18 pin plastic DIP
• Output unlatched at cycle end allows two-dimen-
sional chip selection
• Read-Modify-Write, RAS only refresh, Hidden
refresh, CAS before RAS refresh, and Page Mode
capability.
• All inputs and outputs TTL compatible
• 256 refresh cycles/4ms
BLOCK DIAGRAM
1/02 1/04
1/01 1/03
WR1TE-o-------4{~-------J~
PIN NAMES
Ao-A7
CAS
1/0,-1/04
RAS
WRITE
OE
Vcc
Vss
Address Inputs
Column Address Strobe
Data Input/Output
Row Address Strobe
--
Read/Write Input
Output Enable
-----
-
-_P.._o-w- er-
(+5V)
.---------
-
-
Ground
-----------
AO
Al
A2
A3
A4
A5
A6
A7
- A-71 -
MBMORY
ARRAY
256x256,.,A
1 page  
TMM41464P-12
TMM41464P-15
• READ CYCLE
VIH-----~ ~--------tR~A~S~------I~----------~
RAS tAR
VIL-
tCPN
AO-A?
I~
I-----t~ROH~~JJI//JII/Jfm!II
VOH'-
1/01-1/04
- - - - - - - - - OPEN
o WRITE CYCLE (EARLY WRITE)
VIH -
RAS
VIL-
VIH-
CAS
VIL-
AO-A? VIH-
VIL-
VALID DATA-OUT
I22J Don I t Ca re
VIH-
DE VIL---LLL~~LL~~~~~LL~~~~~~~~~~~~~~~~~~~~~~~~
DHRI
t~ tDH:~VIH-
1/01-1/04
- - - - - - - - - - - VALID DATA- IN - - - - - - -
~VIL-
-_
OPEN
~Don't Care
- A-75 -
5 Page 
TMM41464P-12
TMM41464P-15
APPLICATION INFORMATION
ADDRESSING
The 16 address bits required to decode 1 of the
65,536 cell locations within the TMM41464P are
multiplexed onto the 8 address inputs and latched
into the on-chip address latches by externally apply-
ing two negative going TTL-level clocks.
The first clock, the Row Address Strobe (RAS ),
latches the 8 row address bits into the chip. The
second clock, the Column Address Strobe (CAS) ,
subsequently latches the 8 column address bits into
the chip. Each of these signals, RAS, and CAS,
triggers a sequence of events which are controlled by
different delayed internal clocks.
The two clock chains are linked together logically
in such a way that the address multiplexing operation
is done outside of the critical path timing sequence
for read data access. The later events in the CAS
clock sequence are inhibited until the occurrence of
a delayed signal derived from the RAS clock chain.
This "gated CAS" feature allows the CAS clock to be
externally activated as soon as the Row Address Hold
Time specification (tRAH) has been satisfied and the
address inputs have been changed from Row
address to Column address information.
Data Inputs
Data is written during write or read-modify-write
cycle.
The falling edge of CAS or WRITE strobes data into
the on-chip data latches.
In an early-write cycle, WRITE is brought low prior to
CAS and the data is strobed in by CAS with setup and
hold times referenced to this signal. In delayed write
or read-modify-write cycle, CAS will already be low,
thus the data will be strobed in by WRITE with setup
and hold time referenced to this signal.
In delayed or read-modify-wrile, OE must be high to
bring the output buffers to high impedance prior to
impressing data on the I/O lines.
Data outputs
The three-state output buffers provide direct TTL
compatibility with a fan-out of two standard TTL
loads. Data-out is the same polarity as data-in. The
outputs are in the high-impedance state until CAS is
brought low. In a read cycle the outputs go active
after the access time interval tRAC and tOEA are satis-
fied.
The outputs become valid after the access time
has elapsed and remain valid while CAS and OE are
low. CAS or OE going high returns it to a high
impedance state. In an early-write cycle, the outputs
are always in the high-impedance state. In a delayed
-write or read-modify-write cycle, the outputs will
follow the sequence for the read cycle.
The OE controls the impedance of the output
buffers. In the logic high position the buffers will
remain in a high impedance state
When the OE input is brought to a logic low level,
the output buffers are enabled. Both CAS and bE can
control the outputs. Thus in a read operation, either
OE or CAS returning high forces the outputs into the
high impedance state.
•
RAS ONLY REFRESH
Refresh of the dynamic cell matrix is accom-
plished by performing a memory cycle at each of the
256 row address (Ao-A?) within each 4 millisecond
time interval. Although any normal memory cycle will
perform the refresh operation, this function is most
easily accomplished with "RAS-only" cycles, RAS
only refresh results in a substantial reduction in
operating power. This reduction in power is reflected
in the Icc3 specification.
CAS BEFORE RAS REFRESH
CAS before RAS refreshing available on the
TM M4 1464P offers an alternate refresh method. If
CAS is held on low for the specified period (tCSR)
before RAS goes to low, on chip refresh control
clock generators and the refresh address counter are
enabled, and an internal refresh operation takes
place.
After the refresh operation is performed, the refresh
address counter is automatically incremented in
preparation for the next CAS before RAS refresh
operation.
PAGE MODE
The "Page-Mode" feature of the TMM41464P
allows for successive memory operations at multiple
column locations of the same row address with in-
creased speed without an increase in power. This is
done by strobing the row address into the chip and
maintaining the RAS signal at a logic 0 throughout all
successive memory cycles in which the row address
is common. This "Page-Mode" of operation will not
dissipate the power associated with the negative
A-81 -
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| PDF Descargar | [ Datasheet TMM41464P-15.PDF ] | |
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