TC511001Z-10 Datasheet PDF - Toshiba
| Part Number | TC511001Z-10 | |
| Description | DRAM | |
| Manufacturers | Toshiba | |
| Logo |  |
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TOSHIBA MOS MEMORY PRODUCT
1,048,576 WORDS X 1 BIT DYNAMIC RAM
SILICON GATE CMOS
DESCRIPTION
TC511001 P/J/Z-S5, TC511001 P/J/Z-l0
TC511 001 P/J/Z-12
The TC5ll00lP/J/Z is the new generation dynamic R&~ organized 1,048,576 ~vords by 1
bit. The TC5ll00lP/J/Z utilizes TOSHIBA's caos Silicon gate process technology as well as
advanced circuit techniques to provide wide operating margins, both internally and to the
system user. Multiplexed address inputs permit the TC5ll00lP/J/Z to be packaged in a
standard 18 pin plastic DIP, 26/20 pin plastic SOJ and 20/19 pin plastic ZIP. The package
size provides high system bit "densities and is compatible with widely available automated
testing and insertion equipment. System oriented features include single power supply of
5V±10% tolerance, direct interfacing capability with high performance logic families such
as Schottky TTL. The special feature of TC5Il00IP/J/Z is nibble mode, allowing the user
to serially access 4 bits of data at a high data rate. "Test Mode" function is imple-
mented from RevisionC.
FEATURES
• 1,048,576 words by 1 bit organization
• Fast access time and cycle time
TC5ll00lP/J/Z-8S-10-12
tRAC RAS Access Time
8Sns lOOns l20ns
tAA
Column Address
Access Time
tCAC CAS Access Time
45ns SOns 60ns
30ns 35ns 40ns
tRC Cycle Time
16Sns 190ns 220ns
tNCAC
Nibble
Access
Mocte
Time
trIC
Nibble Mode
Cycle Time
20ns
40ns
20ns
40ns
2Sns
50ns
• Single power supply of SV±lO% with a built-in
VBil generator
PIN CONNECTION (TOP VIEW)
Plastic DIP
Plastic SOJ Plastic ZIP
• Low Power:
38Smt.] MAX. Operating (TC5ll00lP / J /Z-85)
330mW XAX. Operating (TC5ll00lP/J/Z-10)
275mt.; MAX. Operating (TC5ll00lP / J /Z-12)
5.5mW HAX. Standby
• Output unlatched at cycle end allows
two-dimensional chip selection
• Common I/O capability using "EARLY
WRITE" operatior:.
• Read-Modify-t';rite, CAS before RAS re-
fresh, RA'S-only refresh, Hidden refre,<;;l,
Nibble Mode and Test Mode capability
• All inputs and output TTL compatible
• 512 refrewh cycles/8ms
• Package Plastic DIP: TC5ll00lP
Plastic SOJ: TC5ll00lJ
Plastic ZIP: TC5lIOOlZ
BLOCK DIAGRAr~
DIN 1
WRITE
RAS
TP'
A2
A3
Vss
DOUT
CAS
A9
AS
A7
AI5
A~
A4.
~
ftAS
TP'
N.C.
26 Vss
~ ~T
23 N.C.
22 A9
AO AS
Al A7
A2 A6
A:l A5
VCC '---___ ~ A4.
.
AD "'A9
CAS
DIN
DOUT
RAS
WRITE
VCC
VSS
TF
N.C.
Address Inputs
Column Address Strobe
Data In
Data Out
Row Address Strobe
Read/Write Input
Power (+5V)
Ground
Test Function
No Connection
AO
Al
A2
A:l
A~
A5
A6
A7
AS
A9
-A-105 -
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TC511 001 P/J/Z-85, TC511 001 P/J/Z-l 0
TC511001 P/J/Z-12
NOTES:
1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause
permanent damage to the device.
2. All voltage are referenced to Vss.
3. ICCl, I CC3' ICC4, ICC6 depend on cycle rate.
4. ICCl, ICC4 depend on output loading. Specified values are obtained with the
output open.
5. An initial pause of 200~s is required after power-up followed by any 8 ~
cycles before proper device operation is achieved. In case of using internal
refresh counter, a minimum of 8 ~ Before ~ initialization cycles instead
of 8 RAS cycles are required.
6. AC measurements assume tT=5ns.
7. VIH(min.) and VIL(max.) are reference levels for measuring timing of input
Signals. Also, transition times are measured between VIH and VIL. I
8. Measured with a load equivalent to 2 TTL loads and 100pF.
9. tOFF(max.) defines the time at which the output achieves the open circuit
condition and is not referenced to output voltage levels.
10. Either tRCH or tRRH must be satisfied for a read cycle.
11. These parameters are referenced to ~ leading edge in early write cycles and
to WRITE leading edge in read-write cycles.
12. t wcs ' tRWD' tCWD and tAWD are not restrictive operating parameters. They are
included in the data sheet as electrical characteristics only. If twcs ~twcs
(min.), the cycle is an early write cycle and the data out pin will remain
open circuit (high impedance) throughout the entire cycle; If tRWD ~tRWD(min.),
tcwn ~ tcwn(min.) and tAWD ~ tAwn(min.), the cycle is a read-write cycle and the
data out will contain data read from the selected cell: If neither of the above
sets of conditions is satisfied, the condition of the data out (at access time)
is indeterminate.
13. Operation within the tRCn(max.) limit insures that tRAc(max.) can be met.
tRCn(max.) is specified as a reference point only: If tRcn is greater than
the specified tRCn(max.) limit, then access time is controlled by tCAC.
14. Operation within the tRAn(max.) limit insures that tRAC(max.) can be met.
tRAD(max.) is specified as a reference point only: If tRAD is greater than
the specified tRAn(max.) limit, then access tjme is controlled by tAA.
-A-109 -
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