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부품번호 | PN25F16 기능 |
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기능 | 16M-BIT SERIAL FLASH MEMORY | ||
제조업체 | PARAGON | ||
로고 | |||
SPI NOR
PN25F16
PN25F16
16M-BIT SERIAL FLASH MEMORY
Datasheet
Sep. 2015
NOTE: INFORMATION IN THIS PRODUCT SPECIFICATION IS SUBJECT TO CHANGE AT ANYTIME
WITHOUT NOTICE, ALL PRODUCT SPECIFICATIONS ARE PROVIDED FOR REFERENCE ONLY.TO
ANY INTELLECTUAL, PROPERTY RIGHTS IN PARAGON TECHNOLOGY LIMITED. ALL
INFORMATION IN THIS DOCUMENT IS PROVIDED.Web: www.paragontech.cn
A 1.3
5.Block Diagram
SPI NOR
PN25F16
Figure 1 PN25F16 Serial Flash Memory Block Diagram
6.Pin description
During all operations, VCC must be held stable and within the specified valid range: VCC(min) to VCC(max).
Chip Select (/CS)
The chip select signal indicates when a instruction for the device is in process and the other signals are relevant for
the memory device. When the /CS signal is at the logic high state, the device is not selected and all input signals are
ignored and all output signals are high impedance. Unless an internal Program, Erase or Write Status Registers
embedded operation is in progress, the device will be in the Standby Power mode. Driving the /CS input to logic low
state enables the device, placing it in the Active Power mode. After Power Up, a falling edge on /CS is required prior
to the start of any instruction.
Serial Clock (CLK)
This input signal provides the synchronization reference for the SPI interface. Instructions, addresses, or data input
are latched on the rising edge of the CLK signal. Data output changes after the falling edge of CLK.
Serial Input (SI) /IO0
This input signal is used to transfer data serially into the device. It receives instructions, addresses, and data to be
programmed. Values are latched on the rising edge of serial SCK clock signal.
SI becomes IO0 an input and output during Dual and Quad Instructions for receiving instructions, addresses, and
A 1.3
4페이지 8. Device operation
SPI NOR
PN25F16
8.1 Standard SPI Instructions
The PN25F16 features a serial peripheral interface on 4 signals bus: Serial Clock (CLK), Chip Select (/CS), Serial Data
Input (SI) and Serial Data Output (SO). Both SPI bus mode 0 and 3 are supported. Input data is latched on the rising
edge of CLK and data shifts out on the falling edge of CLK.
8.2 Dual SPI Instructions
The PN25F16 supports Dual SPI operation when using the “Dual Output Fast Read” and “Dual I/O Fast Read” (3BH
and BBH) instructions. These instructions allow data to be transferred to or from the device at two times the rate of
the standard SPI. When using the Dual SPI instruction the SI and SO pins become bidirectional I/O pins: IO0 and IO1.
8.3 Quad SPI Instructions
The PN25F16 supports Quad SPI operation when using the “Quad Output Fast Read”, “Quad I/O Fast Read” (6BH,
EBH) instructions. These instructions allow data to be transferred t-o or from the device at four times the rate of the
standard SPI. When using the Quad SPI instruction the SI and SO pins become bidirectional I/O pins: IO0 and IO1,
and /WP and /HOLD pins become IO2 and IO3. Quad SPI instructions require the non-volatile Quad Enable bit (QE)
in Status Register-2 to be set.
8.4 Hold
For dard SPI operation, the HOLD# signal allows the PN25F16 operation to be paused while it is actively selected
(when CS# is low). The HOLD# function may be useful in cases where the SPI data and clock signals are shared with
other devices. For example, consider if the page buffer was only partially written when a priority interrupt requires
use of the SPI bus. In this case the HOLD# function can save the state of the instruction and the data in the buffer so
programming can resume where it left off once the bus is available again.
To initiate a HOLD# condition, the device must be selected with CS# low. A HOLD# condition will activate on the
falling edge of the HOLD# signal if the CLK signal is already low. If the CLK is not already low the HOLD# condition
will activate after the next falling edge of CLK. The HOLD# condition will terminate on the rising edge of the HOLD#
signal if the CLK signal is already low. If the CLK is not already low the HOLD# condition will terminate after the next
falling edge of CLK. During a HOLD# condition, the Serial Data Output (DO) is high impedance, and Serial Data Input
(DI) and Serial Clock (CLK) are ignored. The Chip Select (CS#) signal should be kept active (low) for the full duration
of the HOLD# operation to avoid resetting the internal logic state of the device.
Figure 3 Hold Condition Waveform
A 1.3
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부품번호 | 상세설명 및 기능 | 제조사 |
PN25F16 | 16M-BIT SERIAL FLASH MEMORY | PARAGON |
DataSheet.kr | 2020 | 연락처 | 링크모음 | 검색 | 사이트맵 |