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PDF AD5700-1 Data sheet ( Hoja de datos )
| Número de pieza | AD5700-1 | |
| Descripción | Low Power HART Modem | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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Data Sheet
Low Power HART Modem
AD5700/AD5700-1
FEATURES
GENERAL DESCRIPTION
HART-compliant fully integrated FSK modem
1200 Hz and 2200 Hz sinusoidal shift frequencies
115 µA maximum supply current in receive mode
Suitable for intrinsically safe applications
Integrated receive band-pass filter
Minimal external components required
Clocking optimized for various system configurations
Ultralow power crystal oscillator (60 µA maximum)
External CMOS clock source
Precision internal oscillator (AD5700-1only)
Buffered HART output—extra drive capability
8 kV HBM ESD rating
1.71 V to 5.5 V power supply
1.71 V to 5.5 V interface
−40°C to +125°C operation
4 mm × 4 mm LFCSP package
HART physical layer compliant
UART interface
APPLICATIONS
Field transmitters
HART multiplexers
PLC and DCS analog I/O modules
HART network connectivity
The AD5700/AD5700-1 are single-chip solutions, designed
and specified to operate as a HART® FSK half-duplex modem,
complying with the HART physical layer requirements. The
AD5700/AD5700-1 integrateall of the necessary filtering, signal
detection, modulating, demodulating and signal generation
functions, thus requiring few external components. The 0.5%
precision internal oscillator on the AD5700-1 greatly reduces
the board space requirements, making it ideal for line-powered
applications in both master and slave configurations. The maxi-
mum supply current consumption is 115 µA, making the AD5700/
AD5700-1 an optimal choicefor lowpower loop-powered applica-
tions. Transmit waveforms are phase continuous 1200 Hz and
2200 Hz sinusoids. The AD5700/AD5700-1 contain accurate
carrier detect circuitry and use a standard UART interface.
Table 1. Related Products
Part No. Description
AD5755-1 Quad-channel, 16-bit, serial input, 4 mA to20 mA and
voltage output DAC, dynamic power control, HART
connectivity
AD5421 16-bit, serial input, loop powered, 4 mA to 20 mA DAC
AD5410/ Single-channel, 12-bit/16-bit, serial input, 4 mA to 20 mA
AD5420 current source DACs
AD5412/ Single-channel, 12-bit/16-bit, serial input, current
AD5422 source and voltage output DACs
FUNCTIONAL BLOCK DIAGRAM
REG_CAP
CLKOUT XTAL1 XTAL2 XTAL_EN
VCC
IOVCC
DUPLEX
CD
RXD
TXD
RTS
OSC
FSK
MODULATOR
FSK
DEMODULATOR
AD5700/AD5700-1
DAC
BUFFER
ADC
BAND-PASS
FILTER AND
BIASING
HART_OUT
ADC_IP
HART_IN
CLK_CFG0
CLK_CFG1
VOLTAGE
REFERENCE
RESET
DGND
REF REF_EN
Figure 1.
AGND
FILTER_SEL
Rev. G
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility isassumed by Analog Devicesfor itsuse, norfor any infringementsof patentsor other
rightsof thirdpartiesthatmayresult fromitsuse. Specificationssubjectto changewithout notice.No
licenseisgranted by implication or otherwiseunder any patent or patent rightsof Analog Devices.
Trademarks and registered trademarks are the property oftheir respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-910 6, U.S .A.
Tel: 78 1.32 9.47 00 ©2012–2016 Analog Devices, Inc. All rights reserved.
Technica l Support
www.analog.com
1 page  
Data Sheet
AD5700/AD5700-1
TIMING CHARACTERISTICS
VCC = 1.71 V to 5.5 V, IOVCC = 1.71 V to 5.5 V, TMIN to TMAX, unless otherwise noted.
Table 3.
Parameter 1
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11
Limit at TMIN, TMAX Unit
1 Bit time 2 max
1 Bit time2 max
1 Bit time2 max
6 Bit times2 max
6 Bit times2 max
10 Bit times2 max
2.1 ms typ
6 ms typ
25 µs typ
10 ms typ
30 µs typ
Description
Carrier start time. Time from RTS falling edge to carrier reaching its first peak. See
Figure 3.
Carrier stop time. Time from RTS rising edge to carrier amplitude dropping below
the minimum receive amplitude.
Carrier decay time. Time from RTS rising edge to carrier amplitude dropping to ac
zero. See Figure 4.
Carrier detect on. Time from carrier on to CD rising edge. See Figure 5.
Carrier detect off. Time from carrier off to CD falling edge. See Figure 6.
Carrier detect on when switching from transmit mode to receive mode in the
presence of a constant valid carrier. Time from RTS rising edge to CD rising edge.
See Figure 7.
Crystal oscillator power-up time. On application of a valid power supply voltage at
VCC or on enabling of the oscillator via the XTAL_ EN pin. Crystal load capacitors =
16 pF.
Crystal oscillator power-up time. Crystal load capacitors = 36 pF.
Internal oscillator power-up time. On application of a valid power supply voltage
at VCC or on enabling of the oscillator via the CLK_CFG0 and CLK_CFG1 pins.
Reference power-up time.
Transition time from power-down mode to normal operating mode (external
clock source, external reference).
1 Specifications apply to AD5700/AD5700-1 configured with internal or external receive filter.
2 Bit time is the length of time to transfer one bit of data (1 bit time = 1/1200 Hz = 833.333 µs).
Rev. G | Page 5 of 24
5 Page 
Data Sheet
1.5012
TA = 25°C
1.5010 VCC = IOVCC = 1.71V TO 5.5V
1.5008
1.5006
1.5004
1.5002
1.5000
1.4998
1.4996
1.4994
1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VCC (V)
Figure 15. Reference Voltage vs. VCC
1.5006
1.5004
VCC = IOVCC = 2.7V
TEMPERATURE = –40°C TO +125°C
1.5002
1.5000
1.4998
1.4996
1.4994
1.4992
1.4990
–40 –20
0
20 40 60 80
TEMPERATURE (°C)
100
Figure 16. Reference Voltage vs. Temperature
120
AD5700/AD5700-1
500
TA = 25°C
495
VCC = IOVCC = 3.3V
INT VREF
490
485
1200Hz
2200Hz
480
475 2.2µF
HART_OUT
470
22nF
RLOAD
465
0
200 400 600 800 1000
RLOAD (Ω) || WITH 22nF TO GND
Figure 17. HART_OUT Voltage vs. RLOAD
1200
505
504
TA = 25°C
VCC = IOVCC = 3.3V
503
INT VREF
CAPACITIVE LOAD ONLY
502
501
500
499 1200Hz
498 2200Hz
497
496
495
0
10 20 30 40 50
CLOAD (nF)
Figure 18. HART_OUT Voltage vs. CLOAD
60
Rev. G | Page 11 of 24
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