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PDF TMM2015BP-15 Data sheet ( Hoja de datos )
| Número de pieza | TMM2015BP-15 | |
| Descripción | Static RAM | |
| Fabricantes | Toshiba | |
| Logotipo |  |
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TOSHIBA MOS MEMORY PRODUCTS
2,048 WORD X 8 BIT STATIC RAM TMM2015BP-90, TMM2015BP-12
SILICON MONOLITHIC
TMM2015BP-10, TMM2015BP-15N-CHANNEL SILICON GATE MOS PROCESS
DESCRIPTION
The TMM2015BP is a 16, 384 bits high speed
and low power static random access memory orga-
nized as 2, 048 words by 8 bits and operates from a
single 5V supply. Toshiba's high performance device
technology provides both high speed and low power
features with a maximum access time of 90ns/
100ns/120ns/150ns and maximum operating cur-
rent of 50mA. When CS is a logical high, the device
is placed In a low power standby mode in which
maximum standby current is 5mA. Thus the
TMM201 nBP IS most sUitable for use In microcom-
puter oenpheral memory where the low power
applications are required. The TMM201 5BP IS fa-
bricated with Ion Implanted N channel silicon gate
MOS technology for high performance and high
reliability
FEATURES
• Access Time and Current
Part
~Number
TMM20l5BP-90
TMM20l5BP-l0
TMM20l5BP-12
TMM20l5BP-15
Access
Time
(Max.)
90ns
lOOns
l20ns
l50ns
Operating
Current
(Max.)
50mA
50mA
50mA
50mA
Standby
Current
(Max.)
5mA
5mA
5mA
5mA
• High Density Assembly Capability
0.3 inch width package (24pin plastic DIP)
• Single 5V power Supply
• Fully Static Operation
• Power Down Feature: CS
• Output Buffer Control: OE
o Three State Outputs
• All Inputs and Outputs: Directly TIL Compatible
• Inputs Protected: All Inputs have protection
against static charge.
PIN CONNENCTION
A7
A6
A5
A4
A3
A2
Ai
AO
1/01
1/02
1/03
OND
Vee
A8
A9
WE
OE
AIO
cs
1/08
1/07
1/06
1/05
1/04
PIN NAMES
Ao-A3
A4-AlO
CS
WE
1/0,-1/08
OE
Vee
GND
Column Address Inputs
Row Address Inputs
Chip Select Input
Write Enable Input
Data Input/Output
Output Enable Input
Power (5V)
Ground
BLOCK DIAGRAM
MEMORY
CELL ARRAY
( 128X16X8)
---<> OND
1/01O---~~~==~~--~~---'==~~~---,
1/02 o-----+l-~-I-',
I /0 3 o---.H-~>+.J
! / 0 4 n--_.t++--r>~
1 / 0 5 o - ............I-I-H-~+-J111
1/06 o-~I-I-H--f'>.+-
1/0 7 o--.++++H-n~........J
I /08 D--'I~I-I-H--D--I--
e sU~-_
CSO--~........~
---
-
8-3
WE
OEO------l---l1
1 page  
• (D) WRITE CYCLE (2) (3)
ADDRESSES
TMM2015BP-90, TMM2015BP-12
TMM2015BP-10, TMM2015BP-15
twc
tcw
tos
HIGH
HIGH IMPEDANCE
NOTES:
(1) The WE is high for read cycle.
Device is continuously selected, CS =Vll in read cycle (1)
(2) All addresses are valid perior to or simultaneously with CS transitions.
(3) A write occurs during the overlap of low CS and low WE.
The tew is specified as the time from the chip selection to end of write in write cycle, and the twp is specified as the
overlap time of low CS and low WE.
OE is allowed to be low or high level in write cycle.
If the OE is high, the output buffers remain in a high impedance state in this period.
(4) If the CS low transition occurs simultaneously with or latter to the WE low transition, the output buffers remain in
a high impedance state in this period.
(5) If the CS high transition occurs simultaneously with WE high transition, the output buffers remain in a high
impedance state in this period.
These parameters are specified as follows and measured by using the load shown in Fig. 1.
(A) tClZ. tOlZ. twlZ
Output Enable Time
(8) tCHZ. tOHZ. twHZ
Output Disable Time
--------+~--------------_{f-----------J
(AI
DOUT --......H:.lO:.H~..i.M.P.E.:D.A:N;:C;E..:;.=~---ft--+-UU..1155VV
(Ill
5V
1.8kn
1.u;.:n
Fig. 1 Output load condition for enable disable time measurement.
- 8-7 -
5 Page | ||
| Páginas | Total 6 Páginas | |
| PDF Descargar | [ Datasheet TMM2015BP-15.PDF ] | |
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