|
|
PDF APW7279 Data sheet ( Hoja de datos )
| Número de pieza | APW7279 | |
| Descripción | PMIC | |
| Fabricantes | ANPEC | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de APW7279 (archivo pdf) en la parte inferior de esta página. Total 19 Páginas | ||
|
No Preview Available !
APW7279
PMIC for LED BL + LCD Bias Power
Features
General Description
• 2.7V to 5.5V Input Supply Range
The APW7279 integrates with two high-performance step-
• Current Mode Step-up Regulator (LCD bias)
up converter and two charge pump controllers for TFT-
- 1MHz Fixed Operating Frequency
LCD and Backlight applications. Both the two step-up
- Fast Transient Response
regulators are a current-mode, fixed-frequency PWM
- 18V/700mA ,1.5Ω Internal N-MOS
switching regulator. The 1.0MHz switching frequency al-
• Positive & Negative Charge Pump Driver for VGH, lows the usage of low-profile inductors and ceramic ca-
V
GL
• Current Mode Step-up Regulator (LED BL)
pacitors to minimize the thickness of LCD panel designs.
The charge pump controllers provide regulated the gate-
- 1MHz Fixed Operating Frequency
driver of TFT-LCD VGH and VGL supplies. The APW7279 is
- 0.2V Feedback Voltage
available in a tiny 3mm x 3mm 20-pin TQFN package
- 18V/2A, 0.3Ω internal N-MOS
(TQFN3x3-20).
• Control Output for External P-MOS to Support
• Completely Disconnecting the Battery
• Adjustable Power Sequencing by External
Capacitor
• Internal Soft-Start
• Multiple Overload Protection
• Thermal Shutdown
• Available in Small Package:TQFN3x3-20
Applications
• Tablet PC
Simplified Application Circuit
Step-up Step-up
Converter Converter
For LCD For BL
Positive
Charge
Pump
Negative
Charge
Pump
ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and
advise customers to obtain the latest version of relevant information to verify before placing orders.
Copyright © ANPEC Electronics Corp.
Rev. P.2 - Mar., 2015
1
www.anpec.com.tw
1 page  
APW7279
Electrical Characteristics
Unless otherwise specified, these specifications apply over VIN=3.6V and TA= 25oC.
Symbol
Parameter
Test Conditions
S HUTDOWN
VENH_LCD EN_LCD High Threshold
VEN_LCD Rising
VENL_LCD EN_LCD Low Threshold
VEN_LCD Falling
EN_LCD Leakage Current
VIN = 5V, VEN_LCD = 5V
VE NH_ LED
VE NL_LCD
EN_LED High Threshold
EN_LED Low Threshold
VEN_LED Ris ing
VEN_LED Falling
EN_LED Leakage Current
VIN = 5V, VEN_LED = 5V
CHARGE CURRENT AND INTERNAL SWITCH
ICDLY_ N
CDLY_N Charge Current
CDLY_N High Threshold
VGL Soft-start without Delay from VAVDD
ICDLY_P CDLY_P Charge Current
CDLY_P High Threshold
VGH Soft-start without Delay from VGL
IBSW BSW Pull-down Current
BSW to VIN Ron
RVS SUP to VS On Resistance
SUP to VS Leakage Current
VS Soft-start Duration
(Note 4)
POSITIVE REGULATED CHARGE PUMP
VFBP FBP Regulation Voltage
VIN = 2.7V ~ 5.5V, TA = -40 ~ 85oC
IFBP FBP Input Current
I DRVP
RMS DRVP Output Current
Positive Charge Pump
F requency
VSUP = 12V
T SSP
Positive Charge Pump
Soft-start Duration
(Note 4)
NEGATIVE REGULATED CHARGE PUMP
VFBN FBN Regulation Voltage
VIN=2.7V~5.5V, TA = -40 ~ 85oC
IFBN FBN Input Current
IDRVN
TSSN
RMS DRVN Output Current
Negative Charge Pump
F requency
Negative Charge Pump
Soft-start Duration
VSUP = 12V
(Note 4)
OVER-TEMPERATURE PROTECTION
TOTP
Over-Temperature Protection
(note4)
TJ Rising
Over-Temperature Protection
Hysteresis (note4)
Note 4: Guarantee by design, not production test.
APW7279
Min Typ Max
Un it
--
0.4 -
-1 -
--
0.4 -
-1 -
1V
-V
1 uA
1V
-V
1 uA
- 10 - uA
-1 -V
- 10 - uA
-1 -V
3 5 10 uA
- 200 -
- 50 -
Ω
Ω
- - 100 nA
- 2 - ms
1.22
-50
5
400
-
1.25
-
-
500
2
1.28
50
-
600
-
V
nA
mA
kHz
ms
-25 0
-50 -
5-
25 mV
50 nA
- mA
400 500 600 kHz
- 2 - ms
- 160 -
- 40 -
oC
oC
Copyright © ANPEC Electronics Corp.
Rev. P.2 - Mar., 2015
5
www.anpec.com.tw
5 Page 
APW7279
Function Description
Positive Charge Pump
The positive charge-pump regulator is typically used to
generate the positive supply rail for the TFT LCD gate
driver ICs. The output voltage is set with an external re-
sistive voltage-divider from its output to GND with the
midpoint connected to FBP. The charge pump includes a
high-side p-channel MOSFET(P1) and a low-side n-chan-
nel MOSFET(N1) to control the power transfer as shown
in Figure 1. During the first half-cycle, N1 turns on and
charges flying capacitors C8 (Figure 1). During the sec-
ond half cycle, N1 turns off and P1 turns on, level shifting
C8 by VSUP volts. The amount of charge transferred to the
output is determined by the error amplifier that controls
P1’s on-resistance. The positive charge-pump regulator’s
startup can be delayed by CCDLY_P from negative charge
pump reaches 80% of its normal regulated output voltage,
the positive charge-pump regulator is enabled. Each time
it is enabled, the positive charge-pump regulator goes
through a soft-start routine by ramping up its internal ref-
erence voltage from 0 to 1.25V. The soft-start period is
2ms (typ). The soft-start feature effectively limits the in-
rush current during startup. The t is calculated by
CDLY_P
the following equation.
tCOLY _ P = CCDLY_P
10uA
1.25V
500kHz
VS
C15
P1
VS
C8
SUP
DRVP
N1
GND
VGH
C7
R4
FBP
R5
Fig1. Positive Charge Pump Regulator Block Diagram
Negative Charge Pump
The negative charge-pump regulator is typically used to
generate the negative supply rail for the TFT LCD gate
driver ICs. The output voltage is set with an external re-
sistive voltage-divider from its output to REF with the mid-
point connected to FBN. The number of charge pump
stages and the setting of the feedback divider determine
the output of the negative charge-pump regulator. The
charge-pump controller includes a high-side p-channel
MOSFET (P2) and a low-side n-channel MOSFET (N2) to
control the power transfer as shown in Figure 2.
During the first half cycle, P2 turns on, and flying capaci-
tor C10 charges to VSUP minus a diode drop. During the
second half cycle, P2 turns off, and N2 turns on, level
shifting C10. This connects C10 in parallel with reservoir
capacitor C11. If the voltage across C11 minus a diode
drop is greater than the voltage across C10, charge flows
from C11 to C10 until the diode (D5) turns off. The amount
of charge transferred from the output is determined by
the error amplifier, which controls N2’s on-resistance.
The negative charge-pump regulator is enabled when
the LCD driver step-up regulator reaches 80% of its nor-
mal regulated output voltage and VCDLY_N exceed 1V. Each
time it is enabled, the negative charge-pump regulator
goes through a soft-start routine by ramping down its
internal reference voltage from 1.25V to 0mV. The soft-
start period is 2ms typically. The soft-start feature effec-
tively limits the inrush current during startup. The t is
CDLY_N
calculated by the following equation.
tCOLY _ N = CCDLY_N
10uA
500kHz
SUP
C15
P2
C10
DRVN
N2
GND
D5 VGL
FBN
C11
R6
REF
R7
Fig2. Negative Charge Pump Regulator Block Diagram
Copyright © ANPEC Electronics Corp.
Rev. P.2 - Mar., 2015
11
www.anpec.com.tw
11 Page | ||
| Páginas | Total 19 Páginas | |
| PDF Descargar | [ Datasheet APW7279.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| APW7276 | PMIC | ANPEC |
| APW7277 | Synchronous Boost Converter | ANPEC |
| APW7279 | PMIC | ANPEC |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |