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PDF TMM2018AD-35 Data sheet ( Hoja de datos )
| Número de pieza | TMM2018AD-35 | |
| Descripción | STATIC RAM | |
| Fabricantes | Toshiba | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de TMM2018AD-35 (archivo pdf) en la parte inferior de esta página. Total 6 Páginas | ||
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TOSHIBA MOS MEMORY PRODUCT
2,048 WORD X 8 BIT STATIC RAM
SI LICON MONOLITH IC
N-CHANNEL SILICON GATE MOS PROCESS
TMM2018AO-25, TMM2018AO-35
TMM2018AO-45
IOESCRI PTI ONI
The TMM2018AD is a 16,384 bits high speed and low power static random access
memory organized as 2,048 words by 8 bits and operates from a single 5V supply.
Toshiba's high performance device technology provides both high speed and low power
features with a maximum access time of 25ns/35ns/45ns and maximum operating current
of 150mA/135mA/135mA. When ~ goes high, the device is deselected and placed in a low
power standby mode in which maximum standby current is 20mA.
Thus the TMM2018AD is most suitable for use in cache memory and high speed storage.
The ~12018AD is offered in a 24 pin standard cerdip package with 0.3 inch width for
high density assembly.
The T}~12018AD is fabricated with ion implanted N channel silicon gate MOS technology
for high performance and high reliability.
IFEATURESI
• Fast access time
tACC=25ns: TMH2018AD-25
tACC=35ns: TMM2018AD-35
tACC=45ns: TMM2018AD-45
• Low power dissipation
ICC=150mA: TMr';2018AD-25
ICCc:135mA: TMH2018AD-35
ICC=135mA: TMM2018AD-45
ISB=20mA
• Single 5V power supply
• Fully static operation
• All inputs and outputs
Directly TTL Compatible
• ~ower down feature: CS=VIH
· Output buffer control: OE
• Three state outputs
· Inputs protected: All inputs protection against
static charge.
• Package: 24 pins standard cerdip package, 0.3 inch
width
IPI N CONNECTIONI
A'7
/-.6
1.5
At.
/-.3
A2
101
AO
1/01
1/02
1/0:3
GND
WE
DE
A10
cs
1/08
1/07
1/.-:6
1/05
1/04
IPIN NAMESI
AO-AIO
1/01-1/ 08
~
m
O£
Vee
Gt\D
Address Inputs
Data Input/Output
Chip Select Input
Write Enable Input
Output Enable Input
Power (+5V)
Ground
IBLOCK DIAGRAr~1
A 5 rI...-.L......J ~.---T----,
A6 n..-~~--'
A 7 n..-~..-r--'
A 8 rl...-.L......J ~,.---y----,
A9
A10
MEMORY
CELL ARRAY
( 128X16X8)
--0 Vee
- - 0 OllD
II/O/'20O0-l-f~f-f=::t=--1~f.~..1~lffi~~~~~~~~~~~~~t===~
I/O :3 o----ff1~-+-...I11I
I/O 4 o--~-D--r--' II
I/O 5 o--ritH-D-_+_---' I
I/06O-~~~-+-111
1/07o-~~~-+-~1
I/08o-~~~-+-~
CSo-+---q1"\
WE o-........--aI-J
OEo-+-f-<:~
- C-3 -
1 page  
WRITE CYCLE 2.
Add
TMM2018AO-25, TMM2018AD-35
TMM2018AO-45
twe
tew 'tWR
'tDS
DATA IN STABLE
Note:
1. In read cycle 2, a~l addresses are valid prior to or coincident with
ts transition low.
2. The operating temperature (Ta) is guaranteed with transverse air flow
exceeding 400 linear feet per minute.
- C-7 -
5 Page | ||
| Páginas | Total 6 Páginas | |
| PDF Descargar | [ Datasheet TMM2018AD-35.PDF ] | |
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