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PDF TMM2089P Data sheet ( Hoja de datos )

Número de pieza TMM2089P
Descripción STATIC RAM
Fabricantes Toshiba 
Logotipo Toshiba Logotipo



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No Preview Available ! TMM2089P Hoja de datos, Descripción, Manual

TOSHIBA MOS MEMORY PRODUCT
8,192 WORD X 9 BIT STATIC RAM
N-CHANNEL SILICON GATE MOS
TMM2089p-35, TMM2089P-45
TMM2089p-55
\DESCRIPTION\
The THM2089P is a 73,723 bits high speed N-channel silicon gate MOS static random
access memory organized as ~,192 words by 9 bits and operates from a single 5-volt
supply. The T~lli2089P is features an automatic stand-by mode when deselect by CSI
signal. Thus the TMM2089P is suitable for use in cache memory and high speed storage.
TheTMl'12089P has nine I/O terminals, therefore it is most suitable for MEMORY SYSTEM
with Parity bit. The TMM2089P is offered in a 28 pin standard plastic dual in-line
package with 0.3 inch width for high density assembly.
\FEATURESI
• Access Time and Current
~Part
Number
Acc.ess Operating Standby
Time Current Current
(HAX. ) (HAX. ) (HAX. )
THM2089P-35 35ns l35mA
l5mA
Tt-ll-12089P-45 45ns l35mA
Um2089P-55 55ns l35mA
l5mA
l5mA
• Single 5V Power Supply
• Fully Static Operation
• Pm.Jer Down Feature: (CSI)
• Outpot Buffer Control: (DE)
• Three State Outputs
• All Inputs and Outputs:
(Directly TTL Compatible)
• Inputs Protected:
ISLOCK DIAGRAt-1I
MSB
1112 - Ir----., .------,
{
A5V""""L~~
(All inputs have
protection against
static charge.)
---COND
\PIN COrHlECTIONI
A8
A7
A6
A5
A4
A3
A2
Al
AO
I/O]
1/02
1/03
1/04
GND
Vc
WE
CS2
A9
AIO
All
BE
A12
CBl
1/09
1/08
1/07
,/06
1/05
I/09
IPIN NAr~ESI
AO'VAI2
HE
OE
CSl, CS2
1/01 'V r/09
VCC
GND
Address Inputs
Hrite Enable Input
Output Enable Input
Chip Select Inputs
Data Input/Output
Power (+5V)
Ground
IOPERATION ~10DEI
MODE
Hrite
Read
Standby
Standby
Output Buffer
Disable
- C-49 -
CSI CS2 OE HE 1/01 'V 9
L LH ,,;'~
In
L HL H
Out
H .f- oJ( ,': High-Z
L L ";~ ~': High-Z
L H H H High-Z
Power
Active
Active
Standby
Active
Active

1 page




TMM2089P pdf
TMM2089P-35, TMM2089P-45
TMM2089P-55
HRITE CYCLE 2 (4) (CSl Controlled Hrite)
twc
ADDRESSES
twp
W~
CS2
CSI
DIN
tcw
tcw
tWHZ(5)
High Impedance
tDS
DATA IN STABLE
WRITE CYCLE 3 (4) (CS2 Controlled Hrite)
twc
AD:JkI!.:SSES
WE
CS2
CS I
tcw
tcw
tWHZ (5)
High Impedance
tDS
DATA IN STABLE
- C-53 -

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