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TC57256AD-15 데이터시트 PDF




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부품번호 TC57256AD-15 기능
기능 CMOS ultraviolet light erasable and electrically programmable read only memory
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TC57256AD-15 데이터시트, 핀배열, 회로
TOSHIBA MOS MEMORY PRODUCT
I DESCRIPTIONI
TC57256AD-15
TC57256AD-20
The TC57256AD is a 32,768 word X 8 bit CMOS ultraviolet light erasable and electrically programmable read only memory. For
read operation, the TC57256AD's access time is 150ns. The TC57256AD operates from a single 5-volt power supply and has a low
power standby mode which reduces power dissipation without increasing access time. The standby mode is achieved by applying a
TTL-high level signal to the CE input. Advanced CMOS technology reduces the maximum active current to 40mN6.7MHz and the
standby current to lOOJ.LA. For program operation, the programming is achieved by using the high speed prgramming mode. The
TC57256AD is fabricated using CMOS technology and N-channel silicon double layer gate MOS technology.
IFEATURESI
• Peripheral circuit: CMOS
Memory cell
: N-MOS
Low power dissipation
Active: 40mA/6.7MHz
Standby: lOO~A
• Fast access time:
TC572S6AD-IS lSOns
TCS7256AD-20 200ns
IPIN CONNECTIONI (TOP VIEW)
• Single 5V power supply
• Full static operation
• High speed programming mode
• Inputs and outputs TTL compatible
• Pin compatible with ROMs TC532.57P and
TMM23256P, TMM27256AD and TC57256AD
• Standard 28 pin DIP cerdip package
IBLOCK DIAGRAMI
vpp GND
0001 02 03 04. 05 OG 07
Vpp Vee
A12 A14
A7 A13
AS
A9
All
5E
A2 AlO
Al BE
AO 07
00 06
01 05
02 04
03
AO
Al
A2
A3
A4
A5
A6
A7
AS
A9
AIO
All
A12
A13
A14 U""""""'--_----'
32,76SXSoi ts
IPIN NAr~ESI
AO 'V A14 Address Inputs
00-°7' Outputs (Inputs)
CE Chip Enable Input
~ Output Enable Input
Vpp Program Supply
Voltage
Vce VCC Supply Voltage
(+5V)
GND Ground
IMt~OD~E SlE-- ,tJiljiQi'j] CE OE Vpp
(20) (22) (1)
VCC 00-07
(28' (11 'V 13. 15 'V 19)
POWER
*Read
L
Output Deselect
L
H
5V
SV
Data Out
High Impedance
Active
Standby
H*
High Impedance Standby
Program
LH
Data In
Program Inhibit H H 12.5V 6V High Impedance Active
Program Verify * L
* H or L
Data Out
- 0-73 -




TC57256AD-15 pdf, 반도체, 판매, 대치품
TC57256AD-15
TC57256AD-20
PROGRAM OPERATION
D.C. RECOMMENDED OPERATING CONDITIONS
SYMBOL
PARAMETER
VIH Input High Voltage
VIL Input Low Voltage
VCC Vce Power Supply Voltage
Vpp VPP Power Supply Voltage
NIN.
2.2
-0.3
5.75
12.0
TYP.
-
-
6.0
12.5
MAX.
VCC+1.0
0.8
6.25
13.0
UNIT
V
D.C. and OPERATING CHARACTERISTICS
SYMBOL
PARAMETER
ILl Input Current
VOH Output High Voltage
VOL Output Low Voltage
ICC VCC Supply Current
IpP2 VppSupply Current
Vrn A9 Auto Select Voltage
(Ta=25:!: 5°C, VCC=6V± 0.25V, Vpp=12.5V:!: 0.5V)
TESTCONDITION
VIN=O'V Vce
IOH=-400uA
IOL=2.lmA
-
Vpp=13.0V
-
MIN. TYP. MAX. UNIT
- - :!:10 uA
2.4 - - V
- - 0.4 V
- - 40 mA
- - 50 rnA
1l.5 12.0 12.5 V
A.C. PROGRAMMING CHARACTERISTICS (Ta=25:!: 5°C, VCC=6V:!: O.25V, Vpp=12.5V± 0.5V)
SYMBOL
tAS
tAH
tCES
tCEH
tOES
tDS
tDH
tvps
tvcs
PARAMETER
Address Setup Time
Address Hold Time
CE Setup Time
CE Hold Time
OE Setup Time
Data Setup Time
Data Hold Time
VPP Setup Time
Vec Setup Time
TEST CONDITION MIN. TYP. MAX.
- 2--
- 2--
-
O' -
-
- 0--
- 2--
- 2--
- 2--
- 2--
- 2--
UNIT
us
us
ns
ns
us
us
us
us
us
tpw Initial Program Pulse Width CE=VU, OE=VIH 0.95 1 1.05 ms
topw
tOE
tDFP
Overprogram Pulse Width
OE to Output Valid
OE to Output in High-Z
Note 1
CE=VIH
CE=VIH
2.85 3 78.75 ms
- - 150 ns
- - 130 ns
A.C. TEST CONDITIONS
• Output Load
• Input Pulse Rise and Fall Times
• Input Pulse Levels
• Timing Measurement Reference Level
1 TTL Gate and CL (lOOpF)
IOns Max.
0.45V'\, 2 4V
Input 0.8V and 2.2V, Output 0.8V and 2.0V
Note 1: The length of the overprogram pulse may vary as a function of the counter
value x.
- 0-76 -

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TC57256AD-15 전자부품, 판매, 대치품
TC57256AO-15
TC57256AO-20
ISTANDBY MODEl
The TC57256AD has a low power standby mode controlled by the CE signal.
By applying a high level to the CE input, the TC57256AD is placed in the stan~ mode which reduces the operating
current to IOOIlA. The outputs are in a high impedence state, independent of the OE inputs.
'PROGRAM MODEl
Initially, when received by customers, all bits of the TC57256AD are in the "I" state, which is the erased state.
The programming operation introduces "Os" data into the desired bit locations by electrical programming.
_
The TC57256AD is in the programming mode when the Vpp input is at 12.5V and CE is at TTL-Low under OE=VIH·
The TC57256AD can be programmed at any location, anytime, either individually, sequentially or randomly.
'PROGRAM VERIFY MODEl
The verify mode verifies that the desired data is correctly programmed on the programmed bits.
The verify is accomplished with OE at VIL.
'PROGRAM INHIBIT MODEl
Under the condition that the program voltage (+I2.5V) is applied to Vpp terminal, a high level CE input inhibits the
TC57256AD from being programmed.
Programming of two or more TC57256AD's in parallel with different data is easily accomplished: all inputs except for CE
and OE are commonly connected, a TTL low level program pulse is applied to the CE of the desired device only, and TTL
high level signals are applied to the other devices.
IHIGH SPEED PROGRAMMING MODEl
The program time can be greatly reduced by using this high speed programming mode. The device is set up in the high
speed programming mode when the programming voltage (+I2.5V) is applied to the~p terminal with VCC=6V.
The programming is achieved by applying a single TTL low level Ims pulse to the CE input after addresses and data are
stable. The programmed data is then verified by using the Program Verify Mode.
If the programmed data is not correct, another program pulse of Ims is applied and the programmed data is verified. This
should be repeated until the programmed data is correct. (max. 25 times)
After correctly programming the selected addresses, an additional program pulse with a width of 3 times more than that
needed for initial programming is applied.
When programming has been completed. Data in all addresses should be verified with VCC=Vpp=5V.
- 0-79 -

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부품번호상세설명 및 기능제조사
TC57256AD-15

CMOS ultraviolet light erasable and electrically programmable read only memory

Toshiba
Toshiba

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