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PDF IDT82V2082 Data sheet ( Hoja de datos )
| Número de pieza | IDT82V2082 | |
| Descripción | DUAL CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT | |
| Fabricantes | IDT | |
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DUAL CHANNEL T1/E1/J1 LONG HAUL/
SHORT HAUL LINE INTERFACE UNIT
IDT82V2082
FEATURES:
• Dual channel T1/E1/J1 long haul/short haul line interfaces
• Supports HPS (Hitless Protection Switching) for 1+1 protection
without external relays
• Receiver sensitivity exceeds -36 dB@772KHz and -43
dB@1024 KHz
• Programmable T1/E1/J1 switchability allowing one bill of ma-
terial for any line condition
• Single 3.3 V power supply with 5 V tolerance on digital inter-
faces
• Meets or exceeds specifications in
- ANSI T1.102, T1.403 and T1.408
- ITU I.431, G.703, G.736, G.775 and G.823
- ETSI 300-166, 300-233 and TBR12/13
- AT&T Pub 62411
• Software programmable or hardware selectable on:
- Wave-shaping templates for short haul and long haul LBO (Line
Build Out)
- Line terminating impedance (T1:100 Ω, J1:110 Ω, E1:75 Ω/120
Ω)
- Adjustment of arbitrary pulse shape
- JA (Jitter Attenuator) position (receive path or transmit path)
- Single rail/dual rail system interfaces
- B8ZS/HDB3/AMI line encoding/decoding
DESCRIPTION:
The IDT82V2082canbe configuredasa dualchannelT1,E1orJ1 Line
Interface Unit. In receive path, an Adaptive Equalizer is integrated to
remove the distortion introduced by the cable attenuation. The
IDT82V2082 also performs clock/data recovery, AMI/B8ZS/HDB3 line
decoding and detects and reports the LOS conditions. In transmit path,
there is an AMI/B8ZS/HDB3 encoder, Waveform Shaper and LBOs.
There is one Jitter Attenuator, which can be placed in either the receive
path or the transmit path. The Jitter Attenuator can also be disabled. The
IDT82V2082 supports both Single Rail and Dual Rail system interfaces.
To facilitate the network maintenance, a PRBS/QRSS generation/detec-
- Active edge of transmit clock (TCLK) and receive clock (RCLK)
- Active level of transmit data (TDATA) and receive data (RDATA)
- Receiver or transmitter power down
- High impedance setting for line drivers
- PRBS (Pseudo Random Bit Sequence) generation and detection
with 215-1 PRBS polynomials for E1
- QRSS (Quasi Random Sequence Signals) generation and detec-
tion with 220-1 QRSS polynomials for T1/J1
- 16-bit BPV (Bipolar Pulse Violation) /Excess Zero/PRBS or QRSS
error counter
- Analog loopback, Digital loopback, Remote loopback and Inband
loopback
• Cable attenuation indication
• Adaptive receive sensitivity
• Non-intrusive monitoring per ITU G.772 specification
• Short circuit protection and internal protection diode for line
drivers
• LOS (Loss Of Signal) & AIS (Alarm Indication Signal) detection
• JTAG interface
• Supports serial control interface, Motorola and Intel Non-Mul-
tiplexed interfaces and hardware control mode
• Package:
IDT82V2082: 80-pin TQFP
tion circuit is integrated in the chip, and different types of loopbacks can
be set according to the applications. Four different kinds of line terminating
impedance, 75 Ω, 100 Ω, 110 Ω and 120 Ω are selectable on a per chan-
nel basis. The chipalso provides driver short-circuit protection and internal
protection diode and supports JTAG boundary scanning. The chip can be
controlled by either software or hardware.
The IDT82V2082 can be used in LAN, WAN, Routers, Wireless Base
Stations, IADs, IMAs, IMAPs, Gateways, Frame Relay Access Devices,
CSU/DSU equipment, etc.
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGES
2003 Integrated Device Technology, Inc. All rights reserved.
1
July 2004
DSC-6229/5
1 page  
DUAL CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT
LIST OF TABLES
INDUSTRIAL
TEMPERATURE RANGES
Table-1
Table-2
Table-3
Table-4
Table-5
Table-6
Table-7
Table-8
Table-9
Table-10
Table-11
Table-12
Table-13
Table-14
Table-15
Table-16
Table-17
Table-18
Table-19
Table-20
Table-21
Table-22
Table-23
Table-24
Table-25
Table-26
Table-27
Table-28
Table-29
Table-30
Table-31
Table-32
Table-33
Table-34
Table-35
Table-36
Table-37
Table-38
Table-39
Table-40
Table-41
Table-42
Table-43
Table-44
Table-45
Table-46
Pin Description ................................................................................................................ 9
Transmit Waveform Value For E1 75 Ω ........................................................................ 19
Transmit Waveform Value For E1 120 Ω ...................................................................... 19
Transmit Waveform Value For T1 0~133 ft................................................................... 19
Transmit Waveform Value For T1 133~266 ft............................................................... 20
Transmit Waveform Value For T1 266~399 ft............................................................... 20
Transmit Waveform Value For T1 399~533 ft............................................................... 20
Transmit Waveform Value For T1 533~655 ft............................................................... 20
Transmit Waveform Value For J1 0~655 ft ................................................................... 21
Transmit Waveform Value For DS1 0 dB LBO.............................................................. 21
Transmit Waveform Value For DS1 -7.5 dB LBO ......................................................... 21
Transmit Waveform Value For DS1 -15.0 dB LBO ....................................................... 21
Transmit Waveform Value For DS1 -22.5 dB LBO ....................................................... 22
Impedance Matching for Transmitter ............................................................................ 22
Impedance Matching for Receiver ................................................................................ 23
Criteria of Starting Speed Adjustment........................................................................... 27
LOS Declare and Clear Criteria for Short Haul Mode ................................................... 28
LOS Declare and Clear Criteria for Long Haul Mode.................................................... 29
AIS Condition ................................................................................................................ 29
Criteria for Setting/Clearing the PRBS_S Bit ................................................................ 30
EXZ Definition ............................................................................................................... 33
Interrupt Event............................................................................................................... 37
Global Register List and Map........................................................................................ 38
Per Channel Register List and Map .............................................................................. 39
ID: Device Revision Register ........................................................................................ 40
RST: Reset Register ..................................................................................................... 40
GCF: Global Configuration Register ............................................................................. 40
INTCH: Interrupt Channel Indication Register............................................................... 40
TERM: Transmit and Receive Termination Configuration Register .............................. 41
JACF: Jitter Attenuation Configuration Register ........................................................... 41
TCF0: Transmitter Configuration Register 0 ................................................................. 42
TCF1: Transmitter Configuration Register 1 ................................................................. 42
TCF2: Transmitter Configuration Register 2 ................................................................. 43
TCF3: Transmitter Configuration Register 3 ................................................................. 43
TCF4: Transmitter Configuration Register 4 ................................................................. 43
RCF0: Receiver Configuration Register 0..................................................................... 44
RCF1: Receiver Configuration Register 1..................................................................... 45
RCF2: Receiver Configuration Register 2..................................................................... 46
MAINT0: Maintenance Function Control Register 0...................................................... 46
MAINT1: Maintenance Function Control Register 1...................................................... 47
MAINT2: Maintenance Function Control Register 2...................................................... 47
MAINT3: Maintenance Function Control Register 3...................................................... 47
MAINT4: Maintenance Function Control Register 4...................................................... 48
MAINT5: Maintenance Function Control Register 5...................................................... 48
MAINT6: Maintenance Function Control Register 6...................................................... 48
INTM0: Interrupt Mask Register 0 ................................................................................. 49
5
5 Page 
DUAL CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT
INDUSTRIAL
TEMPERATURE RANGES
Table-1 Pin Description (Continued)
Name
MODE1
MODE0
Type
I
Pin No.
9
10
Description
MODE[1:0]: operation mode of control interface select
The level on this pin determines which control mode is used to control the device as follows:
RCLKE
I
RXTXM1
RXTXM0
I
CS I
LP11
INT O
LP10
I
MODE[1:0]
00
01
10
11
Control Interface mode
Hardware interface
Serial Microcontroller Interface
Motorola non-multiplexed
Intel non-multiplexed
• The serial microcontroller interface consists of CS, SCLK, SCLKE, SDI, SDO and INT pins. SCLKE is used for the
selection of the active edge of SCLK.
• The parallel non-multiplexed microcontroller interface consists of CS, A[5:0], D[7:0], DS/RD, R/W/WR and INT pins.
(Refer to 3.12 MICROCONTROLLER INTERFACES for details)
• Hardware interface consists of PULSn[3:0], THZ, RCLKE, LPn[1:0], PATTn[1:0], JA[1:0], MONTn, TERMn, EQn,
RPDn, MODE[1:0] and RXTXM[1:0] (n=1, 2).
11 RCLKE: the active edge of RCLKn select
In hardware control mode, this pin selects the active edge of RCLKn
• L= update RDPn/RDNn on the rising edge of RCLKn
• H= update RDPn/RDNn on the falling edge of RCLKn
In software control mode, this pin should be connected to GNDIO.
14 RXTXM[1:0]: Receive and transmit path operation mode select
15 In hardware control mode, these pins are used to select the single rail or dual rail operation modes as well as AMI or HDB3/
B8ZS line coding:
• 00= single rail with HDB3/B8ZS coding
• 01= single rail with AMI coding
• 10= dual rail interface with CDR enabled
• 11= slicer mode (dual rail interface with CDR disabled)
In software control mode, these pins should be connected to ground.
42 CS: Chip Select
In serial or parallel microcontroller interface mode, this is the active low enable signal. A low level on this pin enables serial
or parallel microcontroller interface.
LP11/LP10: Loopback mode select for channel 1
When the chip is configured by hardware, this pin is used to select loopback operation modes for channel 1(Inband Loopback
is not provided in hardware control mode)
• 00= no loopback
• 01= analog loopback
• 10= digital loopback
• 11= remote loopback
41 INT: Interrupt Request
In software control mode, this pin outputs the general interrupt request for all interrupt sources. If INTM_GLB bit (GCF, 20H)
is set to ‘1’, all the interrupt sources will be masked. These interrupt sources can be masked individually via registers (INTM0,
13H...) and (INTM1, 14H...). The interrupt status is reported via the registers (INTCH, 21H), (INTS0, 18H...) and (INTS1,
19H...).
Output characteristics of this pin can be defined to be push-pull (active high or active low) or open-drain (active low) by setting
bits INT_PIN[1:0] (GCF, 20H)
LP11/LP10: Loopback mode select for channel 1
See above LP11.
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet IDT82V2082.PDF ] | |
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