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IDT82V2044E 데이터시트 PDF




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부품번호 IDT82V2044E 기능
기능 QUAD CHANNEL T1/E1/J1 SHORT HAUL LINE INTERFACE UNIT
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IDT82V2044E 데이터시트, 핀배열, 회로
QUAD CHANNEL T1/E1/J1
SHORT HAUL LINE INTERFACE UNIT
IDT82V2044E
FEATURES:
• Four channel T1/E1/J1 short haul line interfaces
- High impedance setting for line drivers
• Supports HPS (Hitless Protection Switching) for 1+1 protection
- PRBS (Pseudo Random Bit Sequence) generation and detection
without external relays
with 215-1 PRBS polynomials for E1
• Programmable T1/E1/J1 switchability allowing one bill of ma-
- QRSS (Quasi Random Sequence Signals) generation and detection
terial for any line condition
• Single 3.3 V power supply with 5 V tolerance on digital interfaces
• Meets or exceeds specifications in
- ANSI T1.102, T1.403 and T1.408
- ITU I.431, G.703,G.736, G.775 and G.823
- ETSI 300-166, 300-233 and TBR 12/13
- AT&T Pub 62411
• Per channel software selectable on:
- Wave-shaping templates
- Line terminating impedance (T1:100 , J1:110 Ω, E1:75 Ω/120 Ω)
- Adjustment of arbitrary pulse shape
- JA (Jitter Attenuator) position (receive path or transmit path)
- Single rail/dual rail system interfaces
- B8ZS/HDB3/AMI line encoding/decoding
- Active edge of transmit clock (TCLK) and receive clock (RCLK)
with 220-1 QRSS polynomials for T1/J1
- 16-bit BPV (Bipolar Pulse Violation)/Excess Zero/PRBS or QRSS
error counter
- Analog loopback, Digital loopback, Remote loopback and Inband
loopback
Adaptive receive sensitivity up to -20 dB
Non-intrusive monitoring per ITU G.772 specification
Short circuit protection for line drivers
LOS (Loss Of Signal) detection with programmable LOS levels
AIS (Alarm Indication Signal) detection
JTAG interface
Supports serial control interface, Motorola and Intel Non-Multi-
plexed interfaces
Package:
IDT82V2044E: 128-pin TQFP
- Active level of transmit data (TDATA) and receive data (RDATA)
- Receiver or transmitter power down
DESCRIPTION:
The IDT82V2044E can be configured as a quad T1, quad E1 or quad
J1 Line Interface Unit. The IDT82V2044E performs clock/data recovery,
AMI/B8ZS/HDB3 line decoding and detects and reports the LOS condi-
tions. An integrated Adaptive Equalizer is available to increase the receive
sensitivity and enable programming of LOS levels. In transmit path, there
is an AMI/B8ZS/HDB3 encoder and Waveform Shaper. There is one Jitter
Attenuator for each channel, which can be placed in either the receive path
or the transmit path. The Jitter Attenuator can also be disabled. The
IDT82V2044E supports both Single Rail and Dual Rail system interfaces
and both serial and parallel control interfaces. To facilitate the network
maintenance, a PRBS/QRSS generation/detection circuit is integrated in
each channel, and different types of loopbacks can be set on a per channel
basis. Four different kinds of line terminating impedance, 75, 100 Ω, 110
and 120 are selectable on a per channel basis. The chip also provides
driver short-circuit protection and supports JTAG boundary scanning.
The IDT82V2044E can be used in SDH/SONET, LAN, WAN, Routers,
Wireless Base Stations, IADs, IMAs, IMAPs, Gateways, Frame Relay
Access Devices, CSU/DSU equipment, etc.
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGES
2003 Integrated Device Technology, Inc. All rights reserved.
1
August 2004
DSC-6533/-




IDT82V2044E pdf, 반도체, 판매, 대치품
QUAD CHANNEL T1/E1/J1 SHORT HAUL LINE INTERFACE UNIT
INDUSTRIAL
TEMPERATURE RANGES
3.9
3.10
3.11
3.12
3.13
3.14
3.15
3.8.1 DEFINITION OF LINE CODING ERROR ............................................................... 28
3.8.2 ERROR DETECTION AND COUNTING ................................................................ 28
3.8.3 BIPOLAR VIOLATION AND PRBS ERROR INSERTION ...................................... 29
LINE DRIVER FAILURE MONITORING ........................................................................... 29
MCLK AND TCLK ............................................................................................................. 30
3.10.1 MASTER CLOCK (MCLK) ...................................................................................... 30
3.10.2 TRANSMIT CLOCK (TCLK).................................................................................... 30
MICROCONTROLLER INTERFACES ............................................................................. 31
3.11.1 PARALLEL MICROCONTROLLER INTERFACE................................................... 31
3.11.2 SERIAL MICROCONTROLLER INTERFACE ........................................................ 31
INTERRUPT HANDLING .................................................................................................. 32
5V TOLERANT I/O PINS .................................................................................................. 32
RESET OPERATION ........................................................................................................ 32
POWER SUPPLY ............................................................................................................. 32
4 PROGRAMMING INFORMATION .............................................................................................. 33
4.1 REGISTER LIST AND MAP ............................................................................................. 33
4.2 REGISTER DESCRIPTION .............................................................................................. 35
4.2.1 GLOBAL REGISTERS............................................................................................ 35
4.2.2 JITTER ATTENUATION CONTROL REGISTER ................................................... 37
4.2.3 TRANSMIT PATH CONTROL REGISTERS........................................................... 38
4.2.4 RECEIVE PATH CONTROL REGISTERS ............................................................. 40
4.2.5 NETWORK DIAGNOSTICS CONTROL REGISTERS ........................................... 42
4.2.6 INTERRUPT CONTROL REGISTERS ................................................................... 45
4.2.7 LINE STATUS REGISTERS ................................................................................... 47
4.2.8 INTERRUPT STATUS REGISTERS ...................................................................... 49
4.2.9 COUNTER REGISTERS ........................................................................................ 50
4.2.10 TRANSMIT AND RECEIVE TERMINATION REGISTER ....................................... 51
5 IEEE STD 1149.1 JTAG TEST ACCESS PORT ........................................................................ 52
5.1 JTAG INSTRUCTIONS AND INSTRUCTION REGISTER ............................................... 53
5.2 JTAG DATA REGISTER ................................................................................................... 53
5.2.1 DEVICE IDENTIFICATION REGISTER (IDR) ........................................................ 53
5.2.2 BYPASS REGISTER (BR)...................................................................................... 53
5.2.3 BOUNDARY SCAN REGISTER (BSR) .................................................................. 53
5.2.4 TEST ACCESS PORT CONTROLLER .................................................................. 54
6 TEST SPECIFICATIONS ............................................................................................................ 56
7 MICROCONTROLLER INTERFACE TIMING CHARACTERISTICS ......................................... 68
7.1 SERIAL INTERFACE TIMING .......................................................................................... 68
7.2 PARALLEL INTERFACE TIMING ..................................................................................... 69
4

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IDT82V2044E 전자부품, 판매, 대치품
QUAD CHANNEL T1/E1/J1 SHORT HAUL LINE INTERFACE UNIT
LIST OF FIGURES
INDUSTRIAL
TEMPERATURE RANGES
Figure-1
Figure-2
Figure-3
Figure-4
Figure-5
Figure-6
Figure-7
Figure-8
Figure-9
Figure-10
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Figure-26
Figure-27
Figure-28
Figure-29
Figure-30
Figure-31
Figure-32
Figure-33
Figure-34
Figure-35
Figure-36
Block Diagram ................................................................................................................. 2
IDT82V2044E TQFP128 Package Pin Assignment ........................................................ 8
E1 Waveform Template Diagram .................................................................................. 14
E1 Pulse Template Test Circuit ..................................................................................... 14
DSX-1 Waveform Template .......................................................................................... 14
T1 Pulse Template Test Circuit ..................................................................................... 15
Receive Path Function Block Diagram .......................................................................... 19
Transmit/Receive Line Circuit ....................................................................................... 19
Monitoring Receive Line in Another Chip ...................................................................... 20
Monitor Transmit Line in Another Chip .......................................................................... 20
G.772 Monitoring Diagram ............................................................................................ 21
Jitter Attenuator ............................................................................................................. 22
LOS Declare and Clear ................................................................................................. 23
Analog Loopback .......................................................................................................... 26
Digital Loopback ............................................................................................................ 26
Remote Loopback ......................................................................................................... 26
Auto Report Mode ......................................................................................................... 28
Manual Report Mode ..................................................................................................... 29
TCLK Operation Flowchart ............................................................................................ 30
Serial Processor Interface Function Timing .................................................................. 31
JTAG Architecture ......................................................................................................... 52
JTAG State Diagram ..................................................................................................... 55
Transmit System Interface Timing ................................................................................ 63
Receive System Interface Timing ................................................................................. 63
E1 Jitter Tolerance Performance .................................................................................. 64
T1/J1 Jitter Tolerance Performance .............................................................................. 64
E1 Jitter Transfer Performance ..................................................................................... 66
T1/J1 Jitter Transfer Performance ................................................................................ 66
JTAG Interface Timing .................................................................................................. 67
Serial Interface Write Timing ......................................................................................... 68
Serial Interface Read Timing with SCLKE=1 ................................................................ 68
Serial Interface Read Timing with SCLKE=0 ................................................................ 68
Non_multiplexed Motorola Read Timing ....................................................................... 69
Non_multiplexed Motorola Write Timing ....................................................................... 70
Non_multiplexed Intel Read Timing .............................................................................. 71
Non_multiplexed Intel Write Timing .............................................................................. 72
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부품번호상세설명 및 기능제조사
IDT82V2044

QUAD T1/E1 SHORT HAUL LINE INTERFACE UNIT

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QUAD CHANNEL T1/E1/J1 SHORT HAUL LINE INTERFACE UNIT

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