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PDF IT8772E Data sheet ( Hoja de datos )

Número de pieza IT8772E
Descripción Environment Control - Low Pin Count Input / Output
Fabricantes ITE　
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IT8772E
Environment Control – Low Pin Count Input / Output
(EC - LPC I/O)
Preliminary Specification V0.4
(For F Version)
ITE TECH. INC.
This specification is subject to Change without notice. It is provided “AS IS” and for reference only. For
purchasing information, please contact the nearest ITE TECH sales representatives.
Please note that the IT8772E V0.4 is applicable only to the F version.

1 page




IT8772E pdf
Section
-
Revision History
Revision
Page No.
„ Pin36, pin37, and pin 52 updated
-
„ Chip version updated to "02h"
„ Default of Special Function Selection Register 3 updated to 01h
„ GPIO Set 5, 6 Multi-Function Pin Selection Register (Index=29h,
Default=00h)
¾ Bit 7-6 updated
„ Special Function Selection Register 2 (Index=2Bh,
Default=0000s000h)
¾ Bit 7-3 updated
„ Environment Controller Special Configuration Register (Index=F3h,
Default=00h)
¾ Bit 2-1 updated
„ Special Configuration Register 2 (Index=FBh)
¾ Bit 6-4 updated
„ Watch Dog Timer Configuration Register (Index=72h,
Default=001s0000b)
¾ Bit 5 updated
„ Newly added register
¾ Special FAN Control Mode Extra Vector A, B Range Registers
(Index=93h, 97h, Default=00h)
„ Applied Voltage updated to -0.3V to 3.6V
„ Energy-using Product (EuP) Power Control Signal Timings
¾ Typ. Of "Delay time of AVCC3 falling edge to 5VSB_CTRL#
rising edge." Updated.
„ Power Sequence AC Timing Parameter table updated
„ DSW Timings figure updated
„ DSW Timings Parameter table updated
„ UVP/OVP Detecting Voltage Threshold table updated.
„ Top marking info updated
www.ite.com.tw
A IT8772E V0.4

5 Page





IT8772E arduino
Contents
(Index=93h, 97h, Default=00h) ..............................................................................89
9.5.2.2.59 PCH/AMDTSI Host Status Register (Index=98h, Default=40h) .......89
9.5.2.2.60 PCH/AMDTSI Host Target Address Register (Index=99h, Default=00h)
91
9.5.2.2.61 PCH/AMDTSI Host Command Register (Index=9Ch, Default=00h) 91
9.5.2.2.62 PCH/AMDTSI Write Data Register (Index=9Dh, Default=--h)..........91
9.5.2.2.63 PCH/AMDTSI Host Control Register (Index=9Eh, Default=02h) .....91
9.5.2.2.64 PCH/AMDTSI Read Data (1-16) Register (Index=9Fh, Default=--h)92
9.5.3 Operation ..............................................................................................................................92
9.5.3.1 Power on Reset and Software Reset.......................................................................92
9.5.3.2 Starting Conversion .................................................................................................93
9.5.3.3 Voltage and Temperature Inputs .............................................................................94
9.5.3.4 Layout and Grounding .............................................................................................94
9.5.3.5 Fan Tachometer.......................................................................................................95
9.5.3.6 Interrupt of the EC....................................................................................................95
9.5.3.7 FAN Controller FAN_CTL’s ON-OFF and SmartGuardian Modes ..........................97
9.5.3.8 External Thermal Sensor Programming Procedure.................................................98
9.6 Serial Port (UART) ..........................................................................................................................107
9.6.1 Data Register......................................................................................................................107
9.6.1.1 Receiver Buffer Register (RBR) (Read only, Address offset=0, DLAB=0)............107
9.6.1.2 Transmitter Buffer Register (TBR) (Write only, Address offset=0, DLAB=0) ........107
9.6.2 Control Register..................................................................................................................108
9.6.2.1 Interrupt Enable Register (IER) (Read/Write, Address offset=1, DLAB=0)...........108
9.6.2.2 Interrupt Identification Register (IIR) (Read only, Address offset=2).....................108
9.6.2.3 FIFO Control Register (FCR) (Write Only, Address offset=2) ...............................110
9.6.2.4 Divisor Latches (DLL, DLM) (Read/Write, Address offset=0,1 DLAB=0) ..............110
9.6.2.5 Baud Rate Generator (BRG) .................................................................................110
9.6.2.6 Scratch Pad Register (Read/Write, Address offset=7) ..........................................111
9.6.2.7 Line Control Register (LCR) (Read/Write, Address offset=3) ...............................112
9.6.2.8 Modem Control Register (MCR) (Read/Write, Address offset=4) .........................113
9.6.3 Status Registers .................................................................................................................113
9.6.3.1 Line Status Register (LSR) (Read/Write, Address offset=5) .................................113
9.6.3.2 Modem Status Register (MSR) (Read/Write, Address offset=6) ...........................114
9.6.4 Reset...................................................................................................................................116
9.6.5 Programming ......................................................................................................................116
9.6.6 Software Reset ...................................................................................................................116
9.6.7 Clock Input Operation .........................................................................................................116
9.6.8 FIFO Interrupt Mode Operation ..........................................................................................116
9.7 Keyboard Controller (KBC) .............................................................................................................119
9.7.1 Host Interface .....................................................................................................................119
9.7.2 Data Registers and Status Register ...................................................................................121
9.7.3 Keyboard and Mouse Interface ..........................................................................................121
9.7.4 KIRQ and MIRQ..................................................................................................................121
9.8 Consumer Remote Control (TV Remote) IR (CIR) .........................................................................122
9.8.1 Overview .............................................................................................................................122
9.8.2 Features..............................................................................................................................122
9.8.3 Block Diagram ....................................................................................................................122
9.8.4 Transmit Operation .............................................................................................................124
9.8.5 Receive Operation ..............................................................................................................124
9.8.6 Register Description and Address ......................................................................................124
9.8.6.1 CIR Data Register (DR) .........................................................................................125
9.8.6.2 CIR Interrupt Enable Register (IER) ......................................................................125
9.8.6.3 CIR Receiver Control Register (RCR) ...................................................................127
9.8.6.4 CIR Transmitter Control Register 1 (TCR1) ..........................................................128
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v IT8772E V0.4

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