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UM2148 PDF 데이터시트 : 부품 기능 및 핀배열

부품번호 UM2148
기능 1K x 4 High Speed NMOS SRAM
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UM2148 데이터시트, 핀배열, 회로
(DUMO
========= UM2148
1K x 4 High Speed NMOS SRAM
Features
• 45 ns maximum access time
• No cloS;ks or strobes required
• Automatic CE power down
• Identical cycle and access times
• Single+5V supply 10%)
• Pinout and function compatible to SY2148
• Industry standard 2114 pinout
• Totally TTL compatible all inputs and outputs
• Common data input and output
• High density 18-pin package
• Three-state output
General Description
The UMC UM2148 is a 4096-Bit Static Random Access
Memory organized 1024 words by 4 bits and is fabricated
using UMC's new scaled N-channel silicon.gate technology.
It is designed using fully static circuitry, therefore requiring
no clock or' refreshing to operate. Address set-up times are
not required and the data is read out non-destructively
with the same polarity as the input data. Common data
input and output pins provide maximum design flexibility.
The three-state output facilitates memory expansion by
allowing the outputs to be OR-tied to other devices.
The UM2148 offers an automatic power down feature.
Power down is controlled by the Chip Enable input. When
Chip Enable (CE) goes high, thus deselecting the UM2148
the device will automatically power down and remain in
a standby power mode as long as CE remains high. This
unique feature provides system level power savings as
much as 85%.
The UM2148 is packaged in an 18-pin DIP for ~he highest
possible density. The device is fully TTL compatible and
has a single +5V power supply.
Pin Configuration
Block Diagram
ROW
SELECT
MEMORY ARRAY
64 ROWS
64COLUMNS
-VCC
4-'--- GND
2-8




UM2148 pdf, 반도체, 판매, 대치품
UM2148
Timing Diagrams
READ CYCLE NO.1 (NOTES 3 AND 4)
~"§"---t-AA------------*'------ADDRESS
-----------------tRC ----------------~1.
tOH -
DATAOUT PREVIOUSDATAVALID
DATA VALID
READ CYCLE NO.2 (NOTES 3 AND 5)
14r----------------- tRC ----------------~
HIGH
DATAOUT--~~~~~~~~'~~~r~------D-A-T-A__V_A_L_ID____~--J IMPEDANCE
vcc
SUPPLY
CURRENT
tpuj
ICC - - - - - - -
IS8 - - - - -
WRITE CYCLE NO.1 (WE CONTROLLED) (NOTE 6)
-ADDRESS
1l
twe
tew
~
\ tE:
j"- / / / / / L.L
tAW
tAS
J
l
~twp_ -tWR-
~ \'
J~
DATA IN
r tow
tDH
4- DATA VALID
~E
~twz
~ IMPEDAN~:---------________________________________
I--tow
HIGH
DATA OUT _______...;D;;,,;A..;.T;.;,A..;,...;;U.;,.N_D_E_F_IN_E__D _________)_
~
Notes:
1. Ch ip deselected for greater than 55ns prior to selection.
2. Chip deselected for a finite time that is less than 55ns prior to selection. (If the deselect time is Ons, the chip is by
definition selected and access occurs according to Read Cycle No.1).
3. WE is high for Read Cycles.
4. Device is continuously selected, CE = VI L .
5. Addresses valid prior to or coincident with CE transition low.
6. If CE goes high simultaneously with WE high, the outputs remain in the high impedance state.
7. Transition is measured ± 500mV from low or high impedance voltage with load B. This parameter is sampled and not
10()oA, tested.
8. The operating ambient temperature range is guaranteed with transverse air flow exceeding 400 linear feet per minute.
9. A pullup resistor to Vec on the IT input is required to keep the device deselected: otherwise, power-on current ap-
proaches Icc active.
10. A minimum 0.5 ms time delay is required after application of Vee (+5V) before proper device operation is achieved.
2-11

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