SUMO
UM6116-2/ UM6116-3/ UM6116-4
2K X 8 High Speed CMOS SRAM
Features
• Single 5V supply and high density 24 pin package
• High speed: Fast access time
70ns/90ns/120ns( max.)
• Low power standby and Standby: 5JlW (typ.)
Low power operation
Operation: 250mW (typ.)
• Completely static RAM: No clock or timing strobe
required
• Directly TTL compatible: All input and output
• Pin compatible with standard 16K EPROM/Mask ROM
• Equal access and cycle time
General Description
The UM6116 is a 16,384-bit static random access memory
organized as 2048 words by 8 bits and operates from a
sign Ie 5 volt supply. It is built with UMC's high perform-
ance CMOS process. Six-transistor full CMOS memory cell
provides low standby current and high-reliability. Inputs
and three-state outputs are TTL compatible and allow for
direct interfacing with common system bus structures. The
UM6116 is moulded in a standard 24-pin 600mil-DIP.
Pin Configuration
Block Diagram
A7
A6
As
A4
A3
A2
Al
Ao
1/01
1/02
1/03
GND
vcc
As
A9
WE
OE
A 10
CS
I/Os
1/07
1/06
1/05
1/04
- - - 0 Vec
• MEMORY MATRIX
DECODER •
128 x 128
- - 0 GND
I/Os ()--~--I
•• COLUMN I/O
INPUT
DATA
CONTROL
COLUMN DECODER
WE 0 - - - - ,
CS
2-33
SUMC
Timing Waveform
READ CYCLE (1)(1)(5)
- - - " " \ . ~-----------tRC
ADDRESS
UM6116.2/ UM6116·3/ UM6116·4
READ CYCLE (2)(1 )(2)(4)
0tO" _ADDRESS
00UT
_
_1~I~:===~~~~tto_"A--A_-~_t-R_:C-t-~x-x"~~I._
_~
~
)L
READ CYCLE (3)(1)(3)(4)(5)
ADDRESS
DOUT
Notes:
1. WE is High for Read Cycle.
2. Device is continuously selected, CS = VIL.
3. Address Valid prior to or coincident with CS transition Low.
4. OE =VIL.
5. Transition is measured ±500mV from steady state. This parameter is sampled and not 100% tested.
WRITE CYCLE (1)
- - - " " twc~-------------
ADDRESS
~-----tcw - - - - - - . 1
~~~~~~~~-
,~~~~~~~-
DOUT~~~~~~~*-----------------------~-----------------
DIN------------------------------<
~~----------~~~~~~
2-36
