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Número de pieza | UM6116-5 | |
Descripción | 2K x 8 High Speed CMOS SRAM | |
Fabricantes | UMC | |
Logotipo | ||
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UM6116-5
x 8 High Speed CMOS SRAM
Features
• Single 5V supply and high density 24 pin package
• High speed: Fast access time 55ns (max.)
• Low power standby and
Standby: 5/lW (typ.)
Low power operation
Operation: 250mW (typ.)
• Completely static RAM: No clock or timing strobe
required
• Directly TTL compatible: All input and output
• Pin compatible with standard 16K EPROM/Mask ROM
• Equal access and cycle time
General Description
The UM6116 is a 16,384-bit static random access memory
organized as 2048 words by 8 bits and operates from a
signle 5 volt supply. It is built with UMC~s high perform-
ance CMOS process. Six-transistor full CMOS memory cell
provides low standby current and high-reliability. Inputs
and three-state outputs are TTL compatible and allow for
direct interfacing with common system bus structures. The
UM6116 is moulded in a standard 24-pin600mil-DIP.
Pin Configuration
Block Diagram
A7
A6
As
A4
A3
A2
Al
Ao
1/01
1/0 2
1/03
GND
VCC
As
A9
WE
OE
A 10
CS
I/Os
I/O 7
1/06
1/05
1/04
~u-----t
A10
1/01 0---'--1
I/OS
--aVec
•ROW
MEMORY MATRIX
DECODER •
128 x 128
----0 GND
•• COLUMN I/O
INPUT
DATA
CONTROL
COLUMNDECODER
WE,~----.
2-38
1 page (lDUMC
WRITE CYCLE (2) (1 )(6)
UM6116·5
ADDRESS ------~r~-------------------------' '-__________
01
N
-----------------------------c.
~----~~--~~--
Notes:.
1. WE must be high during all address transitions.
2. A write occurs during the overlap (tWP) of a low CS and a low WE.
3. tWR is measured from the earlier of CS or WE going high to the end of write cycle.
4. During this period, I/O pins are in the output state so that the input signals of opposite phase to the outputs must not be
applied.
5. If the CS low transition occurs simultaneously with the WE low transitions or after the WE transition, outputs remain
in a high impedance state.
6. OE is continuously low (OE = VIL).
7. DOUT is the same phase of write data of this write cycle.
1m8. DOUT .is the read data of next address.
9. If CS is low during this period, pins are in the output state. Then the data input signals of opposite phase to the
outputs must not be applied to them.
10. Transition is measured ±500mV from steady state. This parameter is sampled and not 100% tested.
Data Retention Characteristics over the operating temperature range
Symbol
VDR
leeDR
teDR
tR
Parameter
Vee for Retention Data
Data Retention Current
Chip Deselect to Data Retention Time
Operation Recovery Time
Test Conditions
CS = Vee
VIN = OV or Vee
Vee = 2.0V, CS = Vee
VIN = OV or Vee
Min.
2.0
-
0
tRe (2)
Typ.(1)
-
2
-
-
Max.
-
20
-
-
Units
V
IJ.A
ns
ns
1. Vee =2V, TA =+25°C
2. IRe = Read Cycle Time
Timing Waveform Low Vee Data Retention Waveform
Vee
Data Retention Mode
Ordering Information
Part Number
UM6116-5
UM6116J-5
Access Time (Max.)
55 ns
55 ns
2-42
Package
Plastic
CERDIP
5 Page |
Páginas | Total 5 Páginas | |
PDF Descargar | [ Datasheet UM6116-5.PDF ] |
Número de pieza | Descripción | Fabricantes |
UM6116-2 | 2K x 8 High Speed CMOS SRAM | UMC |
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UM6116-3 | 2K x 8 High Speed CMOS SRAM | UMC |
UM6116-4 | 2K x 8 High Speed CMOS SRAM | UMC |
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