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UM8049 데이터시트 PDF




UMC에서 제조한 전자 부품 UM8049은 전자 산업 및 응용 분야에서
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부품번호 UM8049 기능
기능 Single Chip 8-Bit Microcomputer
제조업체 UMC
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UM8049 데이터시트, 핀배열, 회로
(l)UMC
UM8048 /8035/8049/8039
"llfll''1I1!1iI£~/II'&.illl!~I''ff''~IIII'~!I~'''lr''II.t'j SI·ng.e Ch·IP 8 -BI·t .·I·f.,·crocomputer '1Iftlif"'~
Features
• S-Bit CPu, ROM, RAM, I/O in single package
• Single 5V supply
• Up to 1.36 J1,sec instruction cycle for 11 MHz operation.
All instructions 1 or 2 cycles
• Basic machine instructions: 96
1-byte instructions: 68
2-byte instructions: 2S
• Single level interrupt
General Description
The UMS04S/S035/~049/8039 is a totally self-sufficient
8-bit parallel computer fabricated on a single silicon chip
using UMC N-channel silicon gate MOS process.
The UMS048 contains a 1K x S program memory, a 64 x S
RAM data memory, 27 I/O lines, and an S-bit timer/counter
in addition to on-board oscillator and clock circuits. The
UMS049 contains a 2K x S program memory, a 128 x S
RAM data memory, 27 I/O lines, and an S-bit timer/counter
in qddition to on board oscillator and clock circuits. For
systems· that requ ire extra capabi Iity, the UMS04S/8049
can be expanded using standard memories and MCS-4S,
• UMS04S/8049 is interchangeable with Intel's PS04S/
S049 in pin configuration and electrical characteristics
• UMS049-2Kx8 ROM 12Sx8 RAM 27 I/O Lines
UMS04S-1KxS ROM 64xB RAM 27 I/O Lines
• Internal timer/event counter
• Easily expandable memory and I/O
• Compatible with MCS memory and I/O
MCS-80 and MCS-85 peripherais. The UMS035 is the
equivalent of an UMS04S without program memory. The
UMS039 is the equivalent to an UM8049 without program
memory.
This microprocessor is designed to be an efficient controller
as well as an arithmetic processor. The UMS04S/S049 has
extensive bit handling capability as well as facilities for
both binary and BCD arithmetic. Efficient use of program
memory results from an instruction set consisting mostly of
single byte instructions and non instructions over two
bytes in length.
Pin Con~iguration
TO
XTAL1
XTAL2
RESET
ss
INT
EA
RD
PSEN
WR
ALE
DBo
DBl
DB2
DB3
DB4
DBs
DB6
DB7
VSS
Vee
T!
P27
P26
P25
P24
P17
P16
P15
P14
P13
P12
Pll
Pl0
VDD
PROG
P23
P22
P21
P20
Logic Symbol
XTAL{:
RESET
SINGLE
STEP -
EXTERNAL
MEM-
UM8048!
8049
TEST { :
INTERRUPT -
PORT
=1
PORT
=2
BUS
PORT
EXPANDER
STROBE
3-3




UM8049 pdf, 반도체, 판매, 대치품
A.C. Characteristics
(TA = ooc - 70°C, Vee = voo = +5V ± 10%, Vss = OV)
UM8048/8035/8049/8039
Parameter
Cycle Time
ALE Pulse Width
Address Setup Before ALE
Address Hold From ALE
Control Pulse Width
(RD, WR)
Control Pulse Width
(PSEN)
Data Setup Before WR
Data Hold After WR
Data Hol.d (RD, PSEN)
RD to Data in
PSEN to Data in
Address Setup Before WR·
Address Setup
Before Data in (RD)
Address Setup
Before Data in (PSEN)
Address Float to RD, WR
Address Float to PSEN
Control Pulse ALE
(RD,WR)
Control Pulse to ALE
(PSEN)
Interrupt Pulse Width
Power on Reset Time
Symbol
6MHz
Min. Max.
Limits
8MHz
Min. Max.
11MHz
Min. Max.
Units
Test
Conditions(1)
tCY 2.5 15.0 1.875 15.0 1.36 15.0 J.l.s
tLL 410 270 150
ns
tAL
200
140
70
ns
tLA
120
85
50
ns
tCC1
1050
730
480
ns
tCC2
800
550
350
ns
tDW
880
610
390
ns
tWD
115
75
40
ns
tDR 0 220 0 160 0 110· ns
tRD1
800 520 330 ns
tRD2
550 330
190 ns
tAW
850
470
300
ns
tAD1
1680
1100
730 ns
(2)
tAD2 1250
tAFC1
tAFC2
290
40
tCA1
120
720 460 ns
210
20
..
85
140
10
50
ns
ns
ns
(2)
..
(2)
tCA2
620
460
320
ns
tiNT
3
3
3 MC (3)
..
tRES
5
5
5 MC (3)
3-6

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UM8049 전자부품, 판매, 대치품
(l)UMC
Pin Description
UM8048/8035/8049/8039
Designation
Vss
VDD
Vee
PROG
Port 1:
P10-P17
Port 2:
P24-P27
P20-P23
BUS: DO-D7
TO
T1
TNT
(Active Low)
-
RD
(Active Low)
WR
(Active Low)
RESET
(Active Low)
ALE
PSEN
(Active Low)
SS
(Active Low)
EA
XTAL1
XTAL2
Pin
20
26
40
25
27-34
Functions
Circuit GND Potential
+5V during operation. Low power standby pin
Main power supply; +5V during operation
Output strobe for UM8243 I/O expander
8-bit quasi-bid irectional port
35-38
21-24
12-19
1
39
6
8
10
8-bit quasi-bidirectional port
P20-P23 contain the four high order program counter bits during an external progr.am
fetch and serve as a 4-bit I/O expander bus for UM8243.
True bidirectional port which can be written or read synchronously using the RD, WR
strQbes. The port can also be statically latched. Contains the 8 low order program
counter bits during an external program memory fetch, and receives the addressed
instruction under control of PSEN.
They also contains the address and data during an external RAM data access instruc-
tion under control of ALE, RD, and WR.
Input pin testable using the conditional transfer instructions JTO and JNTO. TO can
be designated as clock output using ENTO CLK instruction.
Input pin testable using the JT1, and JNT1 instructions. Can be designated the timer/
counter input using the STRT CNT Instruction.
Interrupt input. Initiates an interrupt if interrupt is enabled. Interrupt is disabled
after a reset. Also testable with conditional jump instruction. (Active Low)
Output strobe activated during a BUS read. Can be used to enable data onto the BUS
from an external device. Used as a Read Strobe to External Data Memory.
Output strobe during a BUS write. Used as write strobe to External Data Memory.
4 Input which is used to initialize the processor. Also used during verification, and
power down.
11 Address Latch Enable. This signal occurs once during each cycle and is useful as
a clock output. The negative edge of ALE strobes address into external data and
program memory.
9 Program Store Enable. This output occurs only during a fetch to externa'i program
memory.
5 Single step input can be used in conjuction with ALE to "single step" the processor
through each instruction
7 External Access input which for cess all program memory fetches to reference external
memory. Useful for emulation and debug, and essential for testing and program
verification
2 One side of crystal input for internal oscillator Also input for external source.
3 Other side of crystal'input

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