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UM8312 데이터시트 PDF




UMC에서 제조한 전자 부품 UM8312은 전자 산업 및 응용 분야에서
광범위하게 사용되는 반도체 소자입니다.


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부품번호 UM8312 기능
기능 Double Row Buffer
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UM8312 데이터시트, 핀배열, 회로
SUMO
UM8312
Double Row Buffer(DRB)
Features
• Low cost solution to CRT memory contention problem
• Provides enhanced processor throughput for CRT
display systems
• Replaces shift registers or several RAM and counter
IC's in CRT display system
• Permits display of one data row while next data row is
being loaded
• Data may be written into buffer at less than the video
painting rate
• Double data row buffer permits second data row to
be loaded anytime during the display of the preceding
data row
• Permits active video 'on all scan lines of data row
• Dynamically variable numbe~ of characters per data
Row-... 64, 80, 132, .... up to a maximum of 135
• Cascadab Ie for data rows greater than 135 characters
• Stackable for "I nvisible Attributes" or character widths
of greater than 8 Bits
• Three-state outputs
• Up to 4 MHz read/write data rate
• Compatible with UM9007 and other CRT controllers
• 28 pin dual-in-line package
• +5 volt only power supply
• TT L compatible
General Description
The UM8312 Double Row Buffer (ROB) provides a low
cost solution to memory contention between the system
processor and the CRT controller in video display systems.
The UM8312 ORB is a RAM-based buffer which provides
two rows of buffering. It appears to the system as two
octal shift registers of dynamically variable length (2-135
bytes) plus steering logic.
The UM8312 permits the loading of one data row while
the previous data row is being displayed. The loading of
data may take place during any of the scan line times of
the data row. This relaxed time-constraint allows the
processor to perform additional processing on the data or
service other high priority interrupt conditions (such as a
Floopy Disk DMA request) which may occur during a single
video scan line. The result is enhanced processor throughput
and flicker-free display of data.
Pin Configuration
Block Diagram
DIN2
DIN1
DINO
DOUT7
DOUT6
DOUT5
DOUT4
Vcc
DOUT3
DOUT2
DOUT1
DOUTO
DIN7
DIN6
DIN3
WCLK
OE
WEN2
WEN1
GND
ROF
WOF
REN
CLRCNT
TOG
RCLK
DIN4
DIN5
READ/WRITE
CONTROL
TOG
CLRCNT
OE
_RCLK
REN
WCLK
WENl
WEN2
ROF
WOF
5-71




UM8312 pdf, 반도체, 판매, 대치품
SUMC
Operational Description
UMB312
Block diagram illustrates the internal arch itecture of the
UM8312. It contains 135 bytes of RAM in each of its
two buffers. In normal operation, data is written into
the input latch on the positive-going edge of Write Clock
(WCLK). When both Write Enable (WEN1, WEN2) signals
go high, the next WCLK causes data from the input latch
to be written into the selected buffer (lor 2) and the
associated address counter to be incremented by one.
Loading of the selected RAM buffer continues until WEN
goes inactive or until the buffer has been fully loaded. At
the next data row boundary, the Toggle Signal (TOG) will
go low. When Clear Counter (CLRCNT) goes low, the next
Read Clock (RCLK) will begin to reset both buffer address
counters to zero_. switching the buffer just loaded from a
"write buffer" to a "read buffer", permitting the next row
of data to be written into the other buffer. Data from
the current "read" buffer is read out of the buffer and
to the output latch whenever Read Enable (REN) is high
during a Read Clock (RELK). Each read-out from the
buffer RAM causes the "read" address counter to be
incremented. REN is normally high during the entire
visible line time of each scan line of the data row. CLRCNT
resets the present "read'" address counter. The negative
edge of CLRCNT is detected by the UM8312 and the
internal "read" address counter is cleared independent of
the CLRCNT pulse width. The CLRCNT Input may be
tied to the REN input for proper operation.
Figures 1 and 2 illustrate the functional timing for reading
and writing the UM8312. It is possible to cascade two or
more UM8312's to allow for data storage greater than 135
bytes by employing the read overflow (ROF) and write
overflow (WaF) outputs. Figure 3 illustrates two
UM8312's cascaded together.
The UM8312 is compatible with the UM9007 video pro-
cessor and controller (VPACTM) and the UM9021 video
attributes controller (VAC). A typical video configuration
employing the three parts is illustrate in figure 4.
- - - - - - - - - - - - -_--.,..-;..----------------~,\t_,
,_ 1--1
______~
~---J
I
,~_--,.rI~I~---------------~\'~(-------------------
I
II
II
'~6~~~R~¢~'lII/llllij/lI/lIIlf//IIIIIIIIIII!JI I\~-AD-DR-O-----.~"____AD_DR2_'C~II/II!)j/lJ/j!!l!///
l-W_EN_2~J ~IWEN ( = WEN
_ _ _ _ _--:'_ _ _ _ _ _ _
--J!INTERNAL WEN _______________________
DIN7{)/IV7111/i1/i11/l!/i1ll/iI//Tl/ia
~-------~'~'-------------------
~r------l.\'\-t- - - - - - - - - - - - - - - - - - - - - - - - -
~II!II!I/l/I$J!I/I/II!m/
WOF 'lifflIi/ill!IIIIIIIIIIIIA
* in general WCLK and RCLK can be different
,~,- -_ _I
Figure 2. UM8312 Double Row Buffer Write Timing
5-74

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