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UM2661 PDF 데이터시트 : 부품 기능 및 핀배열

부품번호 UM2661
기능 Enhanced Programmable Communications Interface
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UM2661 데이터시트, 핀배열, 회로
(l)UMC
UM2661
Enhanced Programmable
Communications Interface
Features
Synchronous Operation
• 5 to 8-b it characters pi us parity
• Single or double SYN operation
• I nternal or external character synchronization
• Transparent or non-transparent mode
• Transparent mode OLE stuffing (Tx) and detection
(Rx)
• Automatic SYN or DLE-SYN insertion
• SYN, OLE and DLE-SYN stripping
• Odd, even, or no parity
• Local or remote maintenance loop back mode
• Baud rate: dc to 1M bps (1 X clock)
Asynchronous Operation
• 5 to 8-bit characters plus parity
• 1, 1% or 2 stop bit transmitted
• Odd, even, or no parity
• Parity, overrun and framing error detection
• Line break detection and generation
• False start bit detection
• Automatic serial echo mode (echoplex)
• Local or remote maintenance loop back mode
• Baud rate: dc to 1M bps (1 X c~ock)
dc to 62.5K bps (16X clock)
- dc to 15.625K bps (64X clock)
Other Features
• Internal or external baud rate clock
• 3 baud rate sets (2661-1, -2, -3)
• 16 internal rates for each set
• Double buffered transmitter and receiver
• Dynamic character length switching·
• Full or half duplex operation
• TTL compatible inputs and outputs
• RxC and TxC pins are short circuit protected
• 3 open drain MaS outputs can be wire-O Red
• Single 5V power supply
• No system clock required
• 28-pin dual-in-line package
Pin Configuration
Block Diagram
D2
D3
RxD
GND
D4
D5
D6
D7
TxC/SYNC
A1
CE
AO
R/W
RxRDY
D1
DO
VCC
RxC/BKDET
DTR
RTS
DSR
RESET
BRCLK
TxD
TxEMT/DSCHG
CTS
DCD
TxRDY
DATA BUS
00-07
RESET
AO
Al
RNV
CE
ClK
TxC
RxC
OSR
OCO
CTS
RTS
OTR
TxEMT/OSCHG
SYN/OlE
CONTROL
SYNl
REGISTER
SYN2
REGISTER
OLE
REGISTER
TRANSMIT
DATA
HOLDING
REGISTER
TRANSMIT
SHIFT
REGISTER
TxROY
TxO
RECEIVE
SHIFT
REGISTER
RxROY
RxO
7-3




UM2661 pdf, 반도체, 판매, 대치품
SYNCHRONOUS MODE 7-BIT CHARACTER, NO PARITY
RxC
DCD --,~______________________________________________________________________________________________________________________
DSRI
~------------------------------
DTR -----,~___________________________________________________________________________________________________________________
c
In
RxEN ---.J
RxD
LLLL~ I
L~ I I L i
I LJ I I I
II II II
L~ ~AT_A_1__ 1~TA_~ DATA 3
I I I II I
DATA 4
1
n --------------~--~
IIII I I
DATA 5
U UCEIJ
UU
u lJIJ
WRITE ENABLE READ SR
READ SR
READ RxHR
READ RxHR
READ RxHR
READ RxHR READ RxHR
-..J RECEIVER/SET 5TR
DATA 1
DATA 2
DATA 3
DATA 4
DATA 5
eIn RxRDY
~
~
103 ~~------------------------------
SYNDETECT
n
SR BIT 5
_•
~------------------------------------------------------------
ASYNCHRONOUS MODE 7-BIT CHARACTER, NO PARITY, 1 STOP BIT
RxEN ---.J
_ _ _ _..,ti:
I~I
RxD
DATA 1
I~I
DATA 2
I II
DATA 3
MARK
II
I I IDATA 4
DATA 5
I .1...&. ..1_ __
CEU
WRITE ENABLE
RECEIVER/SET 5TIi
RxRDY
U
READ RxHR
DATA 1
U
READ RxHR
UDATA 2
U
READ RxHR
UDATA 3
lJ
READ RxHR
DATA 5
DATA 4 LOST
OVERRUN
SRBIT4 __________________________________________________________________________________________________________~
Figure 1. Receiver Operation Timing Diagram
c:
!
...eft
eft

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UM2661 전자부품, 판매, 대치품
Table 2. Baud Rate Generator Characteristics
2661-1 (BRCLK =4.9152 MHz)
MR2
32
1 0 Baud Rate
00
00
aa
aa
a1
a1
,0 1
01
1a
1a
1a
1a
11
11
11
11
00
01
1a
11
0a
01
1a
11
aa
a1
1a
11
0a
a1
10
11
50
75
110
134.5
150
200
300
600
1050
1200
1800
2000
2400
4800
9600
19200
UM266J.
Actual Frequency
16X Clock (KHz)
0.8
1.2
1.7598
2.152
2.4
3.2
4.8
9.6
16.8329
19.2
28.7438
31.9168
38.4
76.8
153.6
307.2
.
Percent Error
-
-
-0.01
-
-
-
-
-
0.196
-
-0.19
-0.26
-
-
-
-
Divisor
6144
4096
2793
2284
2048
1536
1024
512
292
256
171
154
128
64
32
16
2661-2 (BRCLK =4.9152 MHz)
MR2
32
1
aa
aa
0a
a0
01
a1
a
a
1
1
a
0
01
a1
1a
1a
1a
1
1
0
a
1
10
11
11
1
a
a
11
1
11
1
0
a
1
0
1
a
1
0
1
a
1
a
1
a
1
a
1
Baud Rate
45.5
50
75
110
134.5
150
300
600
1200
1800
2000
2400
4800
9600
19200
38400
Actual Frequency
16X Clock (KHz)
0.7279
0.8
1.2
1.7598
2.152
2.4
4.8
9.6
19.2
28.7438
31.9168
38.4
76.8
153.6
307.2
614.4
Percent Error
0.005
-
-
-0.01
-
-
-
-
-
-0.19
-0.26
-
-
-
-
-
Divisor
6752
6144
4096
2793
2284
2048
1024
512
256
171
154
128
64
32
16
8
2661-3 (BRCLK = 5.0688 MHz)
MR2
32
1
0
Baud Rate
Actual Frequency
16X Clock (KHz)
Percent Error
Divisor
0a
aa
a0
aa
0
a
1
1
01
a1
1a
1a
1a
1a
11
11
11
11
aa
a1
1a
11
0a
a1
1a
11
aa
a1
10
11
aa
a1
1a
11
50
75
110
134.5
150
300
600
1200
1800
2000
2400
3600
4800
7200
9600
19200
0.8
1.2
1.76
2.1523
2.4
4.8
9.6
19.2
28.8
32.081
38.4
57.6
76.8
115.2
153.6
316.8
-
-
-
0.016
-
-
-
-
-
0.253
-
-;
-
-
-
3.126
6336
4224
2880
2355
2112
1056
528
264
176
158
132
88
66
44
33
16
Note: 16X ClK is used in asynchronous mode, In synchronous mode, clock multiplier is 1X and BRG can be used only
for T x C
7-9

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UM2661

Enhanced Programmable Communications Interface

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