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KSZ8081RND 데이터시트 PDF




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부품번호 KSZ8081RND 기능
기능 10BASE-T/100BASE-TX PHY
제조업체 Microchip
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KSZ8081RND 데이터시트, 핀배열, 회로
KSZ8081RNA/RND
10BASE-T/100BASE-TX PHY with RMII
Support
Features
• Single-Chip 10BASE-T/100BASE-TX IEEE 802.3
Compliant Ethernet Transceiver
• RMII v1.2 Interface Support with a 50 MHz Refer-
ence Clock Output to MAC, and an Option to
Input a 50 MHz Reference Clock
• RMII Back-to-Back Mode Support for a 100 Mbps
Copper Repeater
• MDC/MDIO Management Interface for PHY Reg-
ister Configuration
• Programmable Interrupt Output
• LED Outputs for Link and Activity Status Indica-
tion
• On-Chip Termination Resistors for the Differential
Pairs
• Baseline Wander Correction
• HP Auto MDI/MDI-X to Reliably Detect and Cor-
rect Straight-Through and Crossover Cable Con-
nections with Disable and Enable Option
• Auto-Negotiation to Automatically Select the
Highest Link-Up Speed (10/100 Mbps) and
Duplex (Half/Full)
• Power-Down and Power-Saving Modes
• LinkMD® TDR-Based Cable Diagnostics to Iden-
tify Faulty Copper Cabling
• Parametric NAND Tree Support for Fault Detec-
tion Between Chip I/Os and the Board
• HBM ESD Rating (6 kV)
• Loopback Modes for Diagnostics
• Single 3.3V Power Supply with VDD I/O Options
for 1.8V, 2.5V, or 3.3V
• Built-In 1.2V Regulator for Core
• Available in 24-pin 4 mm x 4 mm QFN Package
Target Applications
• Game Consoles
• IP Phones
• IP Set-Top Boxes
• IP TVs
• LOM
• Printers
2016 Microchip Technology Inc.
DS00002199A-page 1




KSZ8081RND pdf, 반도체, 판매, 대치품
KSZ8081RNA/RND
1.0 INTRODUCTION
1.1 General Description
The KSZ8081RNA/RND is a single-supply 10BASE-T/100BASE-TX Ethernet physical-layer transceiver for transmis-
sion and reception of data over standard CAT-5 unshielded twisted pair (UTP) cable.
The KSZ8081RNA/RND is a highly-integrated PHY solution. It reduces board cost and simplifies board layout by using
on-chip termination resistors for the differential pairs and by integrating a low-noise regulator to supply the 1.2V core,
and by offering 1.8/2.5/3.3V digital I/O interface support.
The KSZ8081RNA/RND offers the Reduced Media Independent Interface (RMII) for direct connection to RMII-compliant
MACs in Ethernet processors and switches.
As the power-up default, the KSZ8081RNA/RND uses a 25 MHz crystal to generate all required clocks, including the
50 MHz RMII reference clock output for the MAC. The KSZ8081RND is the version that takes in the 50 MHz RMII ref-
erence clock as the power-up default.
To facilitate system bring-up and debugging in production testing and in product deployment, parametric NAND tree sup-
port enables fault detection between KSZ8081RNA/RND I/Os and the board. LinkMD® TDR-based cable diagnostics
identify faulty copper cabling.
The KSZ8081RNA and KSZ8081RND are available in 24-pin, lead-free QFN packages.
FIGURE 1-1:
SYSTEM BLOCK DIAGRAM
MDC/MDIO
MANAGEMENT
10/100Mbps
RMII MAC
RMII KSZ8081RNA
50MHz
REF_CLK
XO
XI
25MHz
XTAL
22pF
22pF
MEDIA TYPES:
RJ-45
10BASE-T
CONNECTOR 100BASE-TX
DS00002199A-page 4
2016 Microchip Technology Inc.

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KSZ8081RND 전자부품, 판매, 대치품
KSZ8081RNA/RND
TABLE 2-1: SIGNALS - KSZ8081RNA/RND (CONTINUED)
Pin
Number
16
Pin
Name
REF_CLK
Type
Note
2-1
Description
Ipd/O
RMII – 25 MHz Mode: This pin provides the 50 MHz RMII reference clock out-
put to the MAC.
RMII – 50 MHz Mode: This pin is a no connect.
For unmanaged mode (power-up default setting),
– KSZ8081RNA is in RMII – 25 MHz mode and outputs the 50 MHz RMII ref-
erence clock on this pin.
– KSZ8081RND is in RMII – 50 MHz mode and does not use this pin.
After power-up, both KSZ8081RNA and KSZ8081RND can be programmed
to either 25 MHz mode or 50 MHz mode using PHY Register 1Fh Bit [7].
See also XI (Pin 8).
RMII Receive Error Output.
At the de-assertion of reset, this pin needs to latch in a pull-down value for
17
RXER
Ipd/O normal operation. If MAC side pulls this pin high, see Register 16h, Bit [15] for
solution. It is better having an external pull-down resistor to avoid MAC side
pulls this pin high.
18
INTRP
Ipu/ Interrupt Output: Programmable interrupt output. This pin has a weak pull-up,
Opu is open drain, and requires an external 1.0 kpull-up resistor.
19 TXEN I RMII Transmit Enable Input.
20 TXD0 I RMII Transmit Data Input [0] (Note 2-3).
21
TXD1
I/O
RMII Transmit Data Input [1] (Note 2-3).
NAND Tree Mode: NAND Tree output pin.
22
GND
GND Ground.
LED Output: Programmable LED0 Output.
Config. Mode: Latched as auto-negotiation enable (Register 0h, Bit [12]) and
Speed (Register 0h, Bit [13]) at the de-assertion of reset. See the Strapping
Options section for details.
The LED0 pin is programmable using Register 1Fh bits [5:4], and is defined
as follows:
LED Mode = [00]
Link/Activity
23
LED0/
ANEN_SPEED
Ipu/O
No Link
Link
Activity
Pin State
High
Low
Toggle
LED Definition
OFF
ON
Blinking
LED Mode = [01]
Link
No Link
Pin State
High
Link Low
LED Mode = [10], [11]: Reserved
24
RST#
Ipu Chip Reset (active-low).
LED Definition
OFF
ON
2016 Microchip Technology Inc.
DS00002199A-page 7

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