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MLX90805 데이터시트 PDF




Melexis에서 제조한 전자 부품 MLX90805은 전자 산업 및 응용 분야에서
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부품번호 MLX90805 기능
기능 Intelligent Triac Controller
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MLX90805 데이터시트, 핀배열, 회로
MLX90805
Intelligent Triac Controller
Features and Benefits
!" “Soft Start” Eliminates Current Surges
!" Integrated Design Eliminates External Components
!" Drives Virtually Any Resistive or Inductive Load
!" Built–in Thermal Protection
!" Digital Design For Stable Triac Control
!" Immune to Lifetime and Thermal Drift
!" Low Power Consumption
!" 50Hz or 60Hz operation customizable by mask programming
Applications
!" AC Light Dimmer
!" Soft-Start AC Motor Controller
!" Variable-Speed AC Motor Controller
Ordering Information
Part No.
MLX90805
MLX90805
Temperature Suffix
C (0°C to 70°C)
C (0°C to 70°C)
* See Option Code Table for details
Package Code
AA (PDIP-8)
DC (SOIC-8)
Option Code*
CA
CA
1. Functional Diagram
90805
Vss Vdda
Voltage
regulator
Power monitoring
and reset
ZCD
zero
crossing
detector
SET
Vref
ADC
Vref
Lookup
ROM
Vref/2
COMP
Logic
Triac driver
Auto
retriggering
Options
THP
FB
2. Description
The MLX90805 is a power control IC ideally
suited for control of any resistive or inductive
load regulated by a triac.
The chip was designed primarily for starting and
speed control of AC motors, but will work equally
well with any Inductive or resistive load such as
Incandescent lights.
The chip’s primary purpose is to provide a “soft
start” for a motor, preventing current inrush. The
triac is controlled by a linear “ramp” from
minimum to maximum power. Start rate can be
varied from 0.5 sec. to 3 sec, by changing the
option bits.
The secondary function of the MLX90805 is
proper ignition of the triac for inductive and
resistive loads, while keeping the triac’s current
consumption to a minimum.
Added features include a frequency locked loop
for stable ignition point.
3901090805
Rev. 004
Page 1 of 16
Data Sheet
Dec/02




MLX90805 pdf, 반도체, 판매, 대치품
MLX90805
Intelligent Triac Controller
Analog Power-On Reset
This block tracks the voltage applied at VDDA. The triac firing is permitted if VDDA > Vaporh and is
stopped when VDDA < Vaporl.
Parameter
Symbol Test Conditions
Min Typ Max Units
High level threshold
Low level threshold
Hysteresis
Vaporh
Vaporl
Vaphyst
12 13 14 V
9 10 11 V
234V
Zero Cross Detector
This detector contains two comparators with hysteresis. The first comparator has its reference at VDDA.
The reference of the second one is VDDA-1V.
Parameter
Symbol Test Conditions
Min Typ Max Units
High level threshold 1
Low level threshold 1
High level threshold 2
Low level threshold 2
External resistor
Vzc1h
Vzc1l
Vzc2h
Vzc2l
Rzc
Vline = 230VAC typ
VDDA
+0.1
VDDA
-0.1
VDDA
-1.5
VDDA
-2.0
VDDA
+0.25
VDDA
-0.25
VDDA
-2.1
VDDA
-2.6
470
VDDA
+0.4
VDDA
-0.4
VDDA
-2.7
VDDA
-3.2
V
V
V
V
k
Triac (Ignition) Driver
This driver operates as a switch to fire the triac ON. An external switch is needed to imitate the triac gate
current (aprox. 150).
Parameter
Symbol Test Conditions
Min Typ Max Units
Triac gate current
ITRG VDDA > Vaporh
90 mA
ADC
This is a 4-bit ADC.
Parameter
Resolution
Reference voltage
Symbol Test Conditions
VREF
Min Typ Max Units
4
4.6 5
bits
5.4 V
3901090805
Rev. 004
Page 4 of 16
Data Sheet
Dec/02

4페이지










MLX90805 전자부품, 판매, 대치품
MLX90805
Intelligent Triac Controller
ROMi [9 : 0] = ti 2 Fmains 10
With: Fmains = frequency of the mains (in Hz)
Note:
The value should not be negative: very small
values can not be programmed.
The content of the ROM can be defined freely: it
does not need to be linear or continuous. However
for a proper soft start generation under all
conditions, the value with minimum firing angle
(thus maximum speed) must be in the highest
ROM address.
Maximum phase angle
Independent of the phase angle definitions in the
ROM table, a maximum phase angle can be
defined. This is the phase angle that will be applied
immediately after the power on sequence, and is
therefore the first phase angle in the soft start
sequence.
This maximum phase angle is defined in MIN[9:0]
with the formula:
MIN[9:0] = Tini * 2 * Fmains - 10
With:
Tini = the initial phase angle (in msec)
Fmains = frequency of the mains (in Hz)
Default value:
Tini = 7 msec and Fmains = 50Hz, thus MIN[9:0]
is 690.
Soft start time duration
There are 5 bits ATN[4:0] used to define the
duration of the soft start time. The bits can be
calculated with following formula:
Ts = ((Tini – Tmin) * ATTN * 800) / Fmains
With:
Ts = the duration of the soft start (in msec.)
Tini = the initial phase angle defined by MIN[9:0]
(in msec)
Tmin = the phase angle corresponding to the
value in the highest ROM address (in msec).
ATTN = bin2dec(ATN[4:0]+1), a value
between 2 and 32.
Default value:
Tini = 8msec, Tmin = 1.84 msec, ATTN = 32,
thus Ts = 3.15 sec.
Firing pulse duration
The duration of the firing pulses can be defined by
the bits DUTS[1:0] and is equal to
DUT/(1000 * Fmains).
The value of DUT is defined in the following table:
DUTS1
0
0
1
1
DUTS0
0
1
0
1
DUT
16
4
2
1
The default value is 20 usec (for Fmains = 50Hz).
Enable Retriggering
With bit RTRIG set to 1, triac retriggering is
enabled. The retriggering circuit checks whether
the triac is ON, if not additional firing pulses are
generated every 20us (with respect to the end of
the previous firing pulse) until firing of the triac.
With bit RTRIG set to 0, triac retriggering is
disabled. For each triac firing two pulses are
generated with a delay of 20 usec (with respect to
the end of the previous firing pulse).
The default value is triggering enabled.
Retriggering Mask
With the option MINA[3:0] it is possible to define
a zone at the end of each half cycle of the mains
voltage, where it is impossible to generate
retriggering pulses. This has two purposes:
With some (non-inductive) loads the current can
become quite small at the end of each half cycle.
This can eventually activate the retriggering
circuit, which will unnecessarily generate
additional pulses thus increasing the current
consumption.
When generating a retriggering pulse just before
the zero crossing, this pulse could overlap to the
next half period. With some (non-inductive) loads
this can lead to false triggering at full power and
must be avoided.
The bits MINA[3:0] are defined according to the
following formula:
Tmina * 2 * Fmains = MINA[3:0] * 64
With:
Tmina = the phase angle from which retriggering
is prohibited (in msec)
Fmains = frequency of the mains (in Hz)
Default value:
MINA[3:0] = 1101(2) = 13(10) and Fmain = 50Hz,
this means that retriggering is prohibited at
8.32ms.
3901090805
Rev. 004
Page 7 of 16
Data Sheet
Dec/02

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