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UM82C84A 데이터시트 PDF




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부품번호 UM82C84A 기능
기능 CMOS Clock Generator Driver
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UM82C84A 데이터시트, 핀배열, 회로
SUMO
::::====:::CMOS UM82C84A
Clock Generator Driver
Features
• Generates the system clock for CMOS or NMOS
Microprocessors
• Up to 25 MHz operation
• Uses a parallel mode crystal circuit or external frequency
source
• Provides ready synchronization
• Generates system reset output from schm itt trigger
input
• Capable of clock synchronization with other 8284As
• TTL compatible inputs/outputs
• Very low p8wer consumption
• 18 Pi n package
• Single +5V power supply
General Description
The UM82C84A is a high performance CMOS clock
generator-.driver which is designed to service the require-
ments of both CMOS and NMOS microprocessors such as
the 80C86, 80C88, 8086 and the 8088. The chip contains
a crystal controlled oscillator, a divide-by-three counter
and complete "Ready" synchronization and reset logic.
Static CMOS circuit design permits operation with an
external frequency source from DC to 25MHz. Crystal
controlled operation to 25MHz is guaranteed with the
use of a parallel, fundamental mode crystal and two small
load capacitors.
All inputs (except Xl, X2 and RES) are TTL compatible
with a VIH of 2.0 volts over the industrial temperature
and voltage ranges.
Power consumption is a fraction of that of the equivalent
bipolar circuits. This speed-power characteristic of CMOS
permits the designer to custom tailor his system design
with respect to power and/or speed requirements.
Pin Configuration
Block Diagram
CSYNC
PClK
AEN1
RDY1
READY
RDY2
AEN2
ClK
GND
VCC
X1
X2
ASYNC
EFI
Fie
OSC
RES
RESET
Control
Pin
FIC
RES
ROY1
ROY2
AEfIT
AEN2
ASYNC
logical 1
External
Clock
Normal
Bus Ready
Address
Disabled
2 Stage Ready
Synchronization
logical 0
Crystal
Drive
Reset
Bus not
Ready
Address
Enabled
1 Stage Ready
Synchronization
ROY1
ASYNC~--------------------
osc
7-128




UM82C84A pdf, 반도체, 판매, 대치품
UM82C84A
Waveforms
NAME I/O
EFI J\J\.
--- ---tEHEL
OSC
ClK
PClK
CSYNC
RES
o J\J\.
....::::r-..o ~LCLH--- J~4(-____06
...____-r------...o --.r-tCH"1C~H2
-~ -:ttO~L-CL---~,\
ItCLPH-
..,tEHYl - _ - _
~
tYHEH
_tYHYL__~-----
- t plPH - - tpHPL .,..----,.
- -tCLl1H tl1HCl
\I
tCLIL
_
RESET 0
IL
Note: All timing measurements are made at 1.5 volts. Unless otherwise noted.
Figure 2. Waveforms for Clocks and Reset Signals
ClK
RYD1.2-------....l\
AEN1.2----------~
ASYNC--------~
READY------------~
Figure 3. Waveforms for Ready Signals (For Asynchronous Devices)
ClK
RYD1.2 _ _ _ _ _ _ _ _ _~
AEN1.2---------~
ASYNC-------------~
READY-----------~
Figure 4. Waveforms for Ready Signals (For Synchronous Devices)
7-131

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UM82C84A 전자부품, 판매, 대치품
Functional Description
Oscillator
The oscillator circuit of the UM82C84A is designed
primarily for use with an external parallel resonant,
fundamental mode crystal from which the basic operating
frequency is derived.
The crystal frequency should be selected at three times
the required CPU clock. X 1 and X2 are the two crystal
input crystal connections. For the most stable operation
of the oscillator (OSC) output circuit, two capacitors
(Cl = C2) as shown in the waveform figures are recom-
mended. The output of the oscillator is buffered and
br.ought out on OSC so that other system timing signals
can be derived from this stable, crystal-controlled source.
Capacitors Cl, C2 are chosen such that their combined
capacitance:
CT = Cl . C2 (Including stray capacitance)
Cl+C2
matches the load capacitance as specified by the crystal
manufacturer. This insures operation within the frequency
tolerance specified by the crystal manufacturer.
Clock Generator
The clock generator consists of a synchronous divide-by-
three counter with a special clear input that inhibits the
counting.. This clear input (CSYNC) allows the output
clock to be synchronized with an external event (such as
another UM82C84 clock). It is necessary to synchronize
the CSYNC input to the EFI clock external to the
UM82C84A. This is accomplished with two flip-flops.
The counter output is a 33% duty cycle clock at one-third
the input frequency.
The F/C input is a strapping pin that selects either the
crystal oscillator or the EFI input as the clock for the -3
counter. If the EF I input is selected as the clock source,
the oscillator section can be used independently for another
clock source*. Output is taken from OSC.
Clock Outputs
The CLK output is a 33% duty cycle clock driver designed
to drive the 80C86, 80C88 processors directly. PC LK
is a peripheral clock signal whose output frequency is
1/2 that of CLK. PCLK has a 50% duty cycle.
Reset Logic
The reset logic provides a Schmitt trigger input (R ES) and
a synchronizing flip-flop to generate the reset timing.
UM82C84A
The reset signal si synchronized to the falling edge of
CLK. A simple RC network can be used to provide power-
on reset by utilizing this function of the UM82C84A.
Wave-forms for clocks and reset signals are illustrated in
Figure 1.
Ready Synchronization
Two READY inputs (R DY1, R DY2) are provided to
accommodate two system busses. Each input has a
qualifier (AENl and AEN2, respectively). The AEN
signals validate their respective RDY si(:lnals. If a Multi-
Master system is not being used the AEN pin should be
tied LOW.
Synchronization is required for all asynchronous active-
going edges of either RDY input to guarantee that the
RDY setup and hold times are met. Inactive-going edges
of R DY in normally ready systems do not require
synchronization but must satisfy R DY setup and hold as a
matter of proper system design.
The ASYNC input defines two modes of READY
synchronization operation.
When ASYNC is LOW, two stages of synchronization are
provided for active READY input signals. Positive-going
asynchronous READY inputs will first be synchronized
to flip-flop one at the rising edge of ClK (requiring a
setup time tR1VCH) and then synchronized to flip-flop
two at the next falling edge of ClK, after which time the
READY output will go active (H IGH). Negative-going
asynchronous READY inputs will be synchronized directly
to flip-flop two at the falling edge of ClK, after which
time the READY output will go inactive. This mode of
operation is intended for use by asynchronous (normally
not ready) devices in the system wh ich cannot be
guaranteed by design to meet the required RDY setup
timing, tR1VCl, on each bus cycle.
When ASYNC is high or left open, the first READY flip-
flop is bypassed in the READY synchronization logic.
READY inputs are synchronized by flip-flop two on the
falling edge of ClK before they are presented to the
processor. This morie is available for synchronous devices
that can be guaranteed to meet the required RDY setup
time.
ASYNC can be changed on every bus cycle to select the
appropriate mode of synchronization for each device in
the system.
CLOCK
SYNCHRONIZE >--+-----+--1 D
EFI
o
D
Q
Figure 10. CSYNC Synchronization
(TO OTHER 82C84As)
*Note: If EFI input is used, then crystal input Xl must be tied to Vcc or GND and X2 should be left open. If the crystal
inputs are used, then EF I should be tied to Vcc or GND.
7-134

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UM82C84A

CMOS Clock Generator Driver

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