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PDF MXL214C Data sheet ( Hoja de datos )
| Número de pieza | MXL214C | |
| Descripción | Full Spectrum Capture Cable Receiver SoC | |
| Fabricantes | MAXLINEAR | |
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Data Sheet
MxL214C
Full-Spectrum Capture™ Cable Receiver SoC with
Wideband IF Output and Four Transport Stream Outputs
General Description
The MxL214C is a gateway front-end System on a
Chip (SoC) that supports four downstream
DOCSIS channels and four video channels. The
MxL214C targets DOCSIS 2.0/3.0 Video Gateway
designs.
The MxL214C IC captures the full 1GHz cable
bandwidth, and can tune to any eight channels in
the cable spectrum. The IC provides up to four
MPEG Transport Streams (TSs), and up to four
more channels at its wideband IF output.
With its high integration and low-power
consumption, the MxL214C enables a single-chip
DOCSIS 2.0/3.0 and video receiver solution with a
compact board design and low Bill-Of-Materials
(BOM) costs.
The IC is controlled via one of two I2C interfaces
and operates using 3.3V, 1.8V, and 1.1V supplies.
The MxL214C is available in a small, 7mm x 7mm
footprint, 48-pin QFN package.
Applications
High-performance receiver for digital cable
applications such as:
■ DOCSIS 2.0/3.0 and video gateways
■ Fast channel change Digital Transport Adapter
(DTA)
Features
■ Full-Spectrum Capture™ (FSC™) cable
receiver capable of receiving Quadrature
Amplitude Modulation (QAM) channels from
44MHz to 1002MHz, without external Surface
Acoustic Wave (SAW) filters
■ Supports up to eight downstream channels:
– Four serial MPEG TS outputs
– Four channels in a wideband IF output
■ Power consumption of:
– 1.84W in a four-channel video, plus four-
channel IF mode
– 475mW in single-channel Power Save
Mode (PSM)
■ Full cable band power spectrum reporting
■ Configurable PID filtering to support
Autonomous Network Wakeup™
■ Dual I2C-compatible digital control interfaces
allow control from two independent hosts
Supported Standards
The MxL214C is compliant to the following
standards:
■ ITU-T J.83
– Annex A (DVB-C), Annex C
– Annex B (US Cable)
■ DOCSIS 3.0, 2.0
■ EuroDOCSIS 3.0, 2.0
• •MaxLinear Confidential www.maxlinear.com 010-214CDSR01
1 page  
MxL214C Data Sheet
List of Figures
List of Figures
Figure 1: Simplified Block Diagram ............................................................................................................. 1
Figure 2: MxL214C Typical Application ....................................................................................................... 2
Figure 3: Pin Configuration (Top View) ....................................................................................................... 3
Figure 4: MPEG Serial Four-Wire Interface................................................................................................. 5
Figure 5: Voltage Supply Ramp-Up Timing ............................................................................................... 12
Figure 6: 1.8V Supply Ramp-Down Timing ............................................................................................... 12
Figure 7: MPEG Serial Output Timing for Four-Wire TS Mode ................................................................. 13
Figure 8: MPEG Output Rise and Fall Time .............................................................................................. 13
Figure 9: I2C Input Timing ......................................................................................................................... 14
Figure 10: I2C Output Timing .................................................................................................................... 14
Figure 11: Reset Sequence Timing ........................................................................................................... 15
Figure 12: Packaging Dimensions............................................................................................................. 16
Figure 13: I2C AS Configuration using AS Pin 6 ....................................................................................... 18
06/11/14
MaxLinear Confidential
010-214CDSR01
V
5 Page 
MxL214C Data Sheet
Pin Description
MPEG Interface
In the four-wire TS interface, the following four MPEG signals are used to convey information:
■ Clock
■ Data = A serial bit stream that is clocked by MPEG CLK and organized as 188-byte packets.
■ Sync = Asserted concurrent with the first byte (the sync byte) of each packet.
■ Valid = A clock-gating signal that is asserted for the entire 188-byte packet, and de-asserted between
packets for one or more turnaround clock cycles.
The following figure shows the timing waveforms for the four-wire interface.
Figure 4: MPEG Serial Four-Wire Interface
The serial interface has the following features:
■ MPEG clock frequencies are configurable to:
– 112.5MHz
– 84.375MHz
– 56.25MHz
– 42.1875MHz
The configured frequency must be greater than the QAM demodulator data throughput.
■ MPEG data output can be programmed as either MSB first or LSB first.
■ Data may be clocked by either the rising or falling edge of the clock.
■ The polarity of the MPEG Valid and MPEG Sync signals can be inverted.
Table 4: MPEG Serial Four-Wire Interface
Pin Name
MPEG_<0-3>_VAL
MPEG_<0-3>_SYNC
MPEG_<0-3>_DAT
MPEG_CLK
Direction
Output
Output
Output
Output
Mode
Serial
Serial
Serial
Serial
Description
MPEG Valid signal for TS<0-3>.
MPEG Sync signal for TS<0-3>.
MPEG Serial Data for TS<0-3>.
MPEG Clock for TS<0-3>.
06/11/14
MaxLinear Confidential
010-214CDSR01
5
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