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PA28F008SA 데이터시트 PDF




Intel에서 제조한 전자 부품 PA28F008SA은 전자 산업 및 응용 분야에서
광범위하게 사용되는 반도체 소자입니다.


PDF 형식의 PA28F008SA 자료 제공

부품번호 PA28F008SA 기능
기능 8-MBIT (1-MBIT x 8) FlashFile MEMORY
제조업체 Intel
로고 Intel 로고


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PA28F008SA 데이터시트, 핀배열, 회로
28F008SA
8-MBIT (1-MBIT x 8) FlashFileTM MEMORY
Extended Temperature Specifications Included
Y High-Density Symmetrically-Blocked
Architecture
Sixteen 64-Kbyte Blocks
Y Extended Cycling Capability
100 000 Block Erase Cycles
1 6 Million Block Erase
Cycles per Chip
Y Automated Byte Write and Block Erase
Command User Interface
Status Register
Y System Performance Enhancements
RY BY Status Output
Erase Suspend Capability
Y Deep Power-Down Mode
0 20 mA ICC Typical
Y Very High-Performance Read
85 ns Maximum Access Time
Y SRAM-Compatible Write Interface
Y Hardware Data Protection Feature
Erase Write Lockout during Power
Transitions
Y Industry Standard Packaging
40-Lead TSOP 44-Lead PSOP
Y ETOX III Nonvolatile Flash Technology
12V Byte Write Block Erase
Intel’s 28F008SA 8-Mbit FlashFileTM Memory is the highest density nonvolatile read write solution for sol-
id-state storage The 28F008SA’s extended cycling symmetrically blocked architecture fast access time
write automation and low power consumption provide a more reliable lower power lighter weight and higher
performance alternative to traditional rotating disk technology The 28F008SA brings new capabilities to porta-
ble computing Application and operating system software stored in resident flash memory arrays provide
instant-on rapid execute-in-place and protection from obsolescence through in-system software updates
Resident software also extends system battery life and increases reliability by reducing disk drive accesses
For high density data acquisition applications the 28F008SA offers a more cost-effective and reliable alterna-
tive to SRAM and battery Traditional high density embedded applications such as telecommunications can
take advantage of the 28F008SA’s nonvolatility blocking and minimal system code requirements for flexible
firmware and modular software designs
The 28F008SA is offered in 40-lead TSOP (standard and reverse) and 44-lead PSOP packages Pin assign-
ments simplify board layout when integrating multiple devices in a flash memory array or subsystem This
device uses an integrated Command User Interface and state machine for simplified block erasure and byte
write The 28F008SA memory map consists of 16 separately erasable 64-Kbyte blocks
Intel’s 28F008SA employs advanced CMOS circuitry for systems requiring low power consumption and noise
immunity Its 85 ns access time provides superior performance when compared with magnetic storage media
A deep powerdown mode lowers power consumption to 1 mW typical thru VCC crucial in portable computing
handheld instrumentation and other low-power applications The RP power control input also provides
absolute data protection during system powerup down
Manufactured on Intel’s 0 8 micron ETOX process the 28F008SA provides the highest levels of quality
reliability and cost-effectiveness
Other brands and names are the property of their respective owners
Information in this document is provided in connection with Intel products Intel assumes no liability whatsoever including infringement of any patent or
copyright for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products Intel retains the right to make
changes to these specifications at any time without notice Microcomputer Products may have minor variations to this specification known as errata
COPYRIGHT INTEL CORPORATION 1995
November 1995
Order Number 290429-005




PA28F008SA pdf, 반도체, 판매, 대치품
28F008SA
Symbol
A0 – A19
DQ0 – DQ7
CE
RP
OE
WE
RY BY
VPP
VCC
GND
Type
INPUT
INPUT OUTPUT
INPUT
INPUT
INPUT
INPUT
OUTPUT
Table 1 Pin Description
Name and Function
ADDRESS INPUTS for memory addresses Addresses are internally
latched during a write cycle
DATA INPUT OUTPUTS Inputs data and commands during Command
User Interface write cycles outputs data during memory array Status
Register and Identifier read cycles The data pins are active high and
float to tri-state off when the chip is deselected or the outputs are
disabled Data is internally latched during a write cycle
CHIP ENABLE Activates the device’s control logic input buffers
decoders and sense amplifiers CE is active low CE high deselects
the memory device and reduces power consumption to standby levels
RESET DEEP POWERDOWN Puts the device in deep powerdown
mode RP is active low RP high gates normal operation RP also
locks out block erase or byte write operations when active low providing
data protection during power transitions RP active resets internal
automation Exit from Deep Powerdown sets device to read-array mode
OUTPUT ENABLE Gates the device’s outputs through the data buffers
during a read cycle OE is active low
WRITE ENABLE Controls writes to the Command User Interface and
array blocks WE is active low Addresses and data are latched on the
rising edge of the WE pulse
READY BUSY Indicates the status of the internal Write State
Machine When low it indicates that the WSM is performing a block
erase or byte write operation RY BY high indicates that the WSM is
ready for new commands block erase is suspended or the device is in
deep powerdown mode RY BY is always active and does NOT float
to tri-state off when the chip is deselected or data outputs are disabled
BLOCK ERASE BYTE WRITE POWER SUPPLY for erasing blocks of
the array or writing bytes of each block
NOTE
With VPP k VPPLMAX memory contents cannot be altered
DEVICE POWER SUPPLY (5V g10% 5V g5%)
GROUND
4

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PA28F008SA 전자부품, 판매, 대치품
28F008SA
Figure 4 PSOP Lead Configuration
290429 – 19
7

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