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894D115I-01 데이터시트 PDF




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부품번호 894D115I-01 기능
기능 OC-12/STM-4 and OC-3/STM-1 Clock/Data Recovery Device
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894D115I-01 데이터시트, 핀배열, 회로
OC-12/STM-4 and OC-3/STM-1
Clock/Data Recovery Device
894D115I-01
DATA SHEET
General Description
The 894D115I-01 is a clock and data recovery circuit. The device
is designed to extract the clock signal from a NRZ-coded STM-4
(OC-12/STS-12) or STM-1 (OC-3/STS-3) input data signal. The
output signals of the device are the recovered clock and retimed
data signals. Input and output are differential signals for best
signal integrity and to support high clock and data rates. All control
inputs and outputs are single-ended signals. An internal PLL is
used for clock generation and recovery. An external clock input is
provided to establish an initial operating frequency of the clock
recovery PLL and to provide a clock reference in the absence of
serial input data. The device supports a signal detect input and a
lock detect output. A bypass circuit is provided to facilitate factory
tests.
Features
Clock recovery for STM-4 (OC-12/STS-12) and
STM-1 (OC-3/STS-3)
Input: NRZ data (622.08 or 155.52 Mbit/s)
Output: clock signal (622.08MHz or 155.52MHz) and retimed
data signal at 622.08 or 155.52 Mbit/s
Internal PLL for clock generation and clock recovery
Differential inputs can accept LVPECL levels
Differential LVPECL data and clock outputs
Lock reference input and PLL lock output
19.44MHz reference clock input
Full 3.3V supply mode
-40°C to 85°C operating temperature
Available in lead-free (RoHS 6) package
See ICS894D115I for a clock/data recovery circuit with a
TSSOP EPAD package
See ICS894D115I-04 for a clock/data recovery circuit with
LVDS outputs
Block Diagram
CAP
nCAP
DATA_IN Pulldown
nDATA_IN Pullup/Pulldown
REF_CLK Pulldown
STS12 Pulldown
SD Pulldown
LOCK_REFN Pullup
BYPASS Pulldown
PLL
0
1
DATA_OUT
nDATA_OUT
CLK_OUT
nCLK_OUT
LOCK_DET
Pin Assignment
VCCA
DATA_IN
nDATA_IN
VEE_PLL
LOCK_DET
STS12
REF_CLK
LOCK_REFN
VEE
VCC
1
2
3
4
5
6
7
8
9
10
20 VCCA
19 VEE_PLL
18 CAP
17 nCAP
16 BYPASS
15 SD
14 DATA_OUT
13 nDATA_OUT
12 CLK_OUT
11 nCLK_OUT
894D115I-01
20-Lead TSSOP
6.5mm x 4.4mm x 0.925mm
package body
G Package
Top View
894D115I-01 Rev C 2/19/15
1 ©2015 Integrated Device Technology, Inc.




894D115I-01 pdf, 반도체, 판매, 대치품
894D115I-01 DATA SHEET
Table 3. Pin Characteristics
Symbol
Parameter
CIN Input Capacitance
RPULLUP
Input Pullup Resistor
RPULLDOWN Input Pulldown Resistor
Test Conditions
Minimum
Typical
4
51
51
Maximum
Units
pF
k
k
Function Tables
Table 4A. LOCK_DET Operation Table
Operation
The PLL is not locked to the serial input data stream if any of these three conditions occur:
A. Internal oscillator and REF_CLK input frequency are not within 500ppm of each other.
B. SD input is at logic LOW state.
C. LOCK_REFN is at logic LOW state.
When the PLL is locked to the serial input data stream, the CLK_OUT and DATA_OUT signals are valid.
Output
LOCK_DET
LOW
HIGH
Table 4B. STS12 Mode Configuration Table
Input
STS12
Operation
0
STM-1 (OC-3, STS-3) operation. The clock/data recovery circuit attempts to recover the clock from a 155.52 Mbit/s
input data stream. The output clock frequency is 155.52MHz.
1
STM-4 (OC-12, STS-12) operation. The clock/data recovery circuit attempts to recover the clock from a 622.08 Mbit/s
input data stream. The output clock frequency is 622.08MHz.
Table 4C. LOCK_REFN Mode Configuration Table
Input
LOCK_REFN Operation
Lock to reference clock. CLK_OUT/nCLK_OUT output frequency is within ±500ppm of the reference clock
0 (REF_CLK). DATA_OUT is set to logic LOW state and nDATA_OUT is set to logic HIGH state. (DATA_OUT = L,
nDATA_OUT = H).
1 Normal operation.
Table 4D. SD Mode Configuration Table
Input
SD Operation
Indicates a loss-of-signal (LOS) condition to the device. CLK_OUT/nCLK_OUT output frequency is within ±500ppm
0 of the reference clock (REF_CLK). DATA_OUT is set to logic LOW state and nDATA_OUT is set to logic HIGH state.
(DATA_OUT = L, nDATA_OUT = H).
1 Normal operation.
Rev C 2/19/15
4 OC-12/STM-4 AND OC-3/STM-1 CLOCK/DATA RECOVERY DEVICE

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894D115I-01 전자부품, 판매, 대치품
894D115I-01 DATA SHEET
AC Electrical Characteristics
Table 6. AC Characteristics, VCC = 3.3V ± 5%, VEE = 0V, T = -40°C to 85°C
Parameter Symbol
Test Conditions
fVCO
fTOL
VCO Center Frequency
CRU’s Reference Clock
Frequency Tolerance
fTREF_CLK OC-12/STS-12 Capture Range
With respect to the fixed
reference frequency
tLOCK
Acquisition
Lock Time
OC-12/STS-12
Valid REF_CLK and device already
powered-up
JGEN_CLK
Jitter
Generation
CLK_OUT/
nCLK_OUT
14ps rms (max.) jitter on
DATA_IN/nDATA_IN
JTOL
Jitter
Tolerance
OC-12/STS-12;
NOTE 1
Sinusoidal input jitter of DATA_IN/
nDATA_IN from 250kHz to 5MHz
tR / tF
odc
Output Rise/Fall Time; NOTE 1
Output Duty Cycle; NOTE 1
20% to 80%
20% minimum transition density
tS Setup Time; NOTE 1
STS-3
STS-12
tH Hold Time; NOTE 1
STS-3
STS-12
NOTE 1: See diagram in Parameter Measurement Information section.
Minimum Typical Maximum
622.08
-250
250
Units
MHz
ppm
±500
ppm
16 µs
0.005
0.01
UI
0.45
45
2000
450
3000
650
3220
800
3220
800
500
55
UI
ps
%
ps
ps
ps
ps
OC-12/STM-4 AND OC-3/STM-1 CLOCK/DATA RECOVERY DEVICE
7
Rev C 2/19/15

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894D115I-01

OC-12/STM-4 and OC-3/STM-1 Clock/Data Recovery Device

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