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AT28C010-12DK PDF 데이터시트 : 부품 기능 및 핀배열

부품번호 AT28C010-12DK
기능 Space 1-MBit (128K x 8) Paged Parallel EEPROM
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AT28C010-12DK 데이터시트, 핀배열, 회로
Features
Fast Read Access Time – 120 ns
Automatic Page Write Operation
– Internal Address and Data Latches for 128 Bytes
– Internal Control Timer
Fast Write Cycle Time
– Page Write Cycle Time – 10 ms Maximum
– 1 to 128-byte Page Write Operation
Low Power Dissipation
– 50 mA Active Current
– 10 mA CMOS Standby Current
Hardware and Software Data Protection
DATA Polling for End of Write Detection
High Reliability CMOS Technology
– Endurance: 5.104 Read/Modify Write Cycles @ Ground Level
– Data Retention: 10 Years
Operating Range: 4.5V to 5.5V, -55 to +125°C
CMOS and TTL Compatible Inputs and Outputs
No Single Event Latch-up below a LET Threshold of 80 MeV/mg/cm2
Tested up to a Total Dose of (according to MIL STD 883 Method 1019):
– 10 kRads (Si) Read-only Mode when Biased
– 30 kRads (Si) Read-only Mode when Unbiased
JEDEC Approved byte-Wide Pinout
435 Mils Wide 32-Pin Flat Pack Package
AT2010-12DK Mil
Space 1-MBit
(128K x 8)
Paged Parallel
EEPROMs
AT28C010-12DK
Description
The AT28C010-12DK is a high-performance Electrically Erasable and Programmable
Read-Only Memory. Its one megabit of memory is organized as 131,072 words by 8
bits. Manufactured with Atmel’s advanced nonvolatile CMOS technology, the device
offers access times to 120 ns with power dissipation of just 275 mW. When the device
is deselected, the CMOS standby current is less than 10 mA.
The AT28C010-12DK is accessed like a Static RAM for the read or write cycle without
the need for external components. The device contains a 128-byte page register to
allow writing of up to 128 bytes simultaneously. During a write cycle, the address and
1 to 128 bytes of data are internally latched, freeing the address and data bus for
other operations. Following the initiation of a write cycle, the device will automatically
write the latched data using an internal control timer. The end of a write cycle can be
detected by DATA POLLING of I/O7. Once the end of a write cycle has been detected
a new access for a read or write can begin.
Atmel's 28C010 has additional features to ensure high quality in manufacturing. The
device utilizes internal error correction for extended endurance and improved data
retention characteristics. An optional software data protection mechanism is available
to guard against inadvertent writes. The device also includes an extra 128 bytes of
EEPROM for device identification or tracking.
Rev. 4259E–AERO–02/11




AT28C010-12DK pdf, 반도체, 판매, 대치품
Algorithm). After writing the 3-byte command sequence and after tWC the entire AT28C010-
12DK will be protected against inadvertent write operations. It should be noted, that once
protected the host may still perform a byte or page write to the AT28C010-12DK. This is
done by preceding the data to be written by the same 3-byte command sequence used to
enable SDP.
• Once set, SDP will remain active unless the disable command sequence is issued. Power
transitions do not disable SDP and SDP will protect the AT28C010-12DK during power-up
and power-down conditions. All command sequences must conform to the page write timing
specifications. The data in the enable and disable command sequences is not written to the
device and the memory addresses used in the sequence may be written with data in either a
byte or page write operation.
• After setting SDP, any attempt to write to the device without the 3-byte command sequence
will start the internal write timers. No data will be written to the device; however, for the
duration of tWC, read operations will effectively be polling operations.
DEVICE IDENTIFICATION: An extra 128 bytes of EEPROM memory are available to the
user for device identification. By raising A9 to 12V ± 0.5V and using address locations
1FF80H to 1FFFFH the bytes may be written to or read from in the same manner as the
regular memory array.
OPTIONAL CHIP ERASE MODE: The entire device can be erased using a 6-byte software
code. Please see Software Chip Erase application note for details.
DC and AC Operating Range
Operating Temperature (Case)
VDD Power Supply
AT28C010-12DK-12
-55°C to +125°C
5V ± 10%
4 AT28C010-12DK
4259E–AERO–02/11

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AT28C010-12DK 전자부품, 판매, 대치품
AT28C010-12DK
AC Read Characteristics
AC Read Waveforms(1)(2)(3)(4)
ADDRESS
ADDRESS VALID
ADDRESS VALID
CE
OE
OUTPUT
TELQV
TAVQV
TELQVPH
TOLQV
TAVQV
TEHQZ
TAXQX
HIGH Z
OUTPUT VALID
TELQV
TOLQV
TAVQV
TEHQZ
TAXQX
HIGH Z
OUTPUT VALID
Notes:
1. CE may be delayed up to TAVQV - TELQV after the address transition without impact on TAVQV.
2. OE may be delayed up to TELQV - TOLQV after the falling edge of CE without impact on TELQV or
by TAVQV - TOLQV after an address change without impact in TAVQV.
3. TEHQZ is specified from OE or CE wichever occurs first (CL = 5 pF).
4. This parameter is characterized and is not 100% tested.
5. If CE is de-asserted, it must remain de-asserted for at least 50ns during read operations other-
wise incorrect data may be read.
4259E–AERO–02/11
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부품번호상세설명 및 기능제조사
AT28C010-12DK

Space 1-MBit (128K x 8) Paged Parallel EEPROM

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