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PDF EM47EM3288MBA Data sheet ( Hoja de datos )
| Número de pieza | EM47EM3288MBA | |
| Descripción | 8Gb Double DATA RATE 3 SDRAM | |
| Fabricantes | Eorex | |
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EM47EM3288MBA
8Gb (32M×8Bank×32) Double DATA RATE 3 Stack SDRAM
Features
• VDD/VDDQ = 1.35V -0.065/+0.1V.
• Backward compatible to VDD = VDDQ = 1.5V
±0.075V.Supports DDR3L devices to be backward
compatible in 1.5V applications.
• Fully differential clock inputs (CK, /CK) operation.
• Eight Banks
• Posted CAS by programmable additive latency
• Bust length: 4 with Burst Chop (BC) and 8.
• CAS Write Latency (CWL): 5,6,7,8
• CAS Latency (CL): 5,6,7,8,9,10
• Write Latency (WL) =Read Latency (RL) -1.
• Bi-directional Differential Data Strobe (DQS).
• Data inputs on DQS centers when write.
• Data outputs on DQS, /DQS edges when read.
• On chip DLL align DQ, DQS and /DQS transition
with CK transition.
• DM mask write data-in at the both rising and falling
edges of the data strobe.
• Sequential & Interleaved Burst type available both
for 8 & 4 with BC.
• Multi Purpose Register (MPR) for pre-defined
pattern read out
• On Die Termination (ODT) options: Synchronous
ODT, Dynamic ODT, and Asynchronous ODT
• Auto Refresh and Self Refresh
• 8,192 Refresh Cycles / 64ms
• Refresh Interval: 7.8us Tcase between 0°C ~ 85°C
• Refresh Interval: 3.9us Tcase between 85°C ~ 95°C
• RoHS Compliance
• Driver Strength:RZQ/7, RZQ/6 (RZQ=240Ω)
• High Temperature Self-Refresh rate enable
• ZQ calibration for DQ drive and ODT
• RESET pin for initialization and reset function
Description
The EM47EM3288MBA is a high speed stack
multi-chip package integrated 4Gbits x2 DDR3L
SDRAM and fabricated with ultra high performance
CMOS process containing 8G bits which organized
as 32Mbits x 8 banks by 32 bits. This synchronous
device achieves high speed double-data-rate transfer
rates of up to 1600 Mb/sec/pin (DDR3L-1600) for
general applications. The chip is designed to comply
with the following key DDR3L SDRAM features: (1)
posted CAS with additive latency, (2) write latency =
read latency -1, (3) On Die Termination (4)
programmable driver strength data,(5) seamless BL4
access. All of the control and address inputs are
synchronized with a pair of externally supplied
differential clocks. Inputs are latched at the cross
point of differential clocks (CK rising and /CK falling).
All I/Os are synchronized with a pair of bidirectional
differential data strobes (DQS and /DQS) in a source
synchronous fashion. The address bus is used to
convey row, column and bank address information in
a /RAS and /CAS multiplexing style. The 8Gb DDR3L
devices operates with a single power supply: 1.35V
±1.35V -0.065/+0.1V or 1.5V ± 0.075V VDD and
VDDQ. Available package with RoHS compliance:
FBGA-136Ball (14 x 12 x 1.4 mm)
Apr. 2014
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1 page  
EM47EM3288MBA
Ball Description (Continued)
D3,D10,P10,P3
D4,D9,P9,P4
G4,G3,J4
C4,C9,R9,R4
DQS0~3,
/DQS0~3
RAS ,
CAS ,
WE
DM0
~DM3
(Data Strobe)
Output with read data, input with write data. Edge aligned with read
data, centered with write data. The data strobes DQS are paired with
differential signals /DQS, respectively, to provide differential pair
signaling to the system during both reads and writes. DDR3L SDRAM
supports differential data strobe only and does not support
single-ended.
(Command Inputs)
RAS , CAS & WE (along with CS ) define the command being
entered.
(Input Data Mask)
DM is input mask signal for write data. Input data is masked when
DM are sampled HIGH coincident with that input data during a write
access. DM is sampled on both edges of DQS.
B2,A4,C2,B4,E2,E4,F2,F
4,B11,A9,C11,B9,E11,E9
,F11,F9,M11,M9,N11,N9,
R11,T9,T11,U9,M2,M4,N
2,N4,R2,T4,T2,U4
A1,G1,L1,U1,A12,
G12,L12,U12,/F1,
M1,A2,J2,U2,A11,
J11,U11,F12,M12
B1,C1,R1,T1,D2,P2,E3,F
3,M3,N3,E10,F10,M10,N
10,D11,P11,B12,C12,R1
2,T12/D1,E1,N1,P1,A3,B
3,C3,R3,T3,U3,
A10,B10,C10,R10,T10,U
10,D12,E12,N12,P12
J3,J10
DQ0~31
VDD/VSS
VDDQ/
VSSQ
ZQ0~1
(Data Input/Output)
Data inputs and outputs are on the same pin.
(Power Supply/Ground)
VDD and VSS are power supply for internal circuits.
(DQ Power Supply/DQ Ground)
VDDQ and VSSQ are power supply for the output buffers.
(ZQ Calibration)
Reference pin for ZQ calibration, ZQ0 for DQ0~15(Die1) and ZQ1 for
DQ16~31(Die2).
(Active Low Asynchronous Reset)
H1
J1
J12
G2,H11,H12
RESET
VREFDQ
VREFCA
NC
Reset is active when RESET is LOW, and inactive when RESET
is HIGH. RESET must be HIGH during normal operation. RESET
is a CMOS rail to rail signal with DC high and low at 80% and 20% of
VDD, i.e. 1.20V for DC high and 0.30V for DC low.
(Reference Voltage)
Reference voltage for DQ
(Reference Voltage)
Reference voltage for CA
(No Connection)
No internal electrical connection is present.
Note: Input pins only BA0-BA2, A0-A13, RAS , CAS , WE , CS , CKE, ODT and RESET do not supply
termination.
Apr. 2014
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5 Page 
EM47EM3288MBA
AC and DC Output Measurement Levels
Symbol Parameter
Specification Units Note
VOH(DC)
VOM(DC)
VOL(DC)
VOH(AC)
VOL(AC)
VOHdiff(DC)
VOLdiff(DC)
DC output high measurement level (for IV curve linearity)
DC output middle measurement level (for IV curve linearity)
DC output low measurement level (for IV curve linearity)
AC output high measurement level (for output slew rate)
AC output low measurement level (for output slew rate)
AC differential output high measurement level (for output
slew rate)
AC differential output low measurement level (for output
slew rate)
0.8*VDDQ
0.5*VDDQ
0.2*VDDQ
VTT+0.1*VDDQ
VTT-0.1*VDDQ
0.2*VDDQ
-0.2*VDDQ
V
V
V
V
V
V
V
1
1
2
2
Notes1. The swing of ±0.1 × VDDQ is based on approximately 50% of the static single-ended output high or
low swing with a driver impedance of 34Ω and an effective test load of 25Ω to VTT = VDDQ/2 at each of the
differential outputs.
Notes2. The swing of ±0.2 × VDDQ is based on approximately 50% of the static single-ended output high or
low swing with a driver impedance of 34Ω and an effective test load of 25Ω to VTT = VDDQ/2 at each of the
differential outputs.
DQS Output Crossing Voltage - VOX (DDR3L-1600 or Higher Speed Bin)
Symbol
Parameters
DQS, /DQS differential slew rate
5V/ns 6V/ns 7V/ns 8V/ns 9V/ns
VOX (AC) max.
VOX (AC) min.
Deviation of DQS,
/DQS output
cross point
voltage from
0.5*VDDQ
+100
-100
+120
-120
+140
-140
+160
-160
+180
-180
10V/ns
+200
-200
11V/ns
+200
-200
12V/ns
+200
-200
Unit
mV
mV
DQS Output Crossing Voltage - VOX (DDR3L-1333 or Lower Speed Bin)
Symbol
Parameters
DQS, /DQS differential slew rate
5V/ns 6V/ns 7V/ns 8V/ns 9V/ns
VOX (AC) max.
VOX (AC) min.
Deviation of DQS,
/DQS output
cross point
voltage from
0.5*VDDQ
+125
-125
+150
-150
+175
-175
+200
-200
+225
-225
10V/ns
+225
-225
11V/ns
+225
-225
12V/ns
+225
-225
Unit
mV
mV
Notes1. Measured using an effective test load of 25Ωto 0.5*VDDQ at each of the differential outputs.
Notes2. For a differential slew rate in between the listed values, the VOX value may be obtained by linear
interpolation.
Notes3. The DQS, /DQS pins under test are not required to be able to drive each of the slew rates listed in the
table; the pins under test will provide one VOX value when tested with specified test condition. The DQS and
/DQS differential slew rate when measuring VOX determines which VOX limits to use.
Apr. 2014
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