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EM488M1644VBB 데이터시트 PDF




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부품번호 EM488M1644VBB 기능
기능 128Mb Synchronous DRAM
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EM488M1644VBB 데이터시트, 핀배열, 회로
eorex
EM488M1644VBB
128Mb (2M×4Bank×16) Synchronous DRAM
Features
• Fully Synchronous to Positive Clock Edge
• Single 2.75V ~ 3.6V Power Supply
• LVTTL Compatible with Multiplexed Address
• Programmable Burst Length (B/L) - 1, 2, 4, 8
or Full Page
• Programmable CAS Latency (C/L) - 2 or 3
• Data Mask (DQM) for Read / Write Masking
• Programmable Wrap Sequence
– Sequential (B/L = 1/2/4/8/full Page)
– Interleave (B/L = 1/2/4/8)
• Burst Read with Single-bit Write Operation
• All Inputs are Sampled at the Rising Edge of
the System Clock
• Auto Refresh and Self Refresh
• 4,096 Refresh Cycles / 64ms (15.625us)
Ordering Information
Description
The EM488M1644VBB is Synchronous Dynamic
Random Access Memory (SDRAM) organized as
2Meg words x 4 banks by 16 bits. All inputs and
outputs are synchronized with the positive edge of
the clock.
The 128Mb SDRAM uses synchronized pipelined
architecture to achieve high speed data transfer
rates and is designed to operate at 3.3V low power
memory system. It also provides auto refresh with
power saving / down mode. All inputs and outputs
voltage levels are compatible with LVTTL.
Available packages:TFBGA-54B(8mmx8mm).
Part No
Organization Max. Freq
EM488M1644VBB-75F
8M X 16
133MHz @CL3
EM488M1644VBB-7F
8M X 16
143MHz @CL3
EM488M1644VBB-75FE
8M X 16
133MHz @CL3
EM488M1644VBB-7FE
8M X 16
143MHz @CL3
EM488M1644VBB-75
8M X 16
133MHz @CL3
EM488M1644VBB-7
8M X 16
143MHz @CL3
Package
TFBGA -54B
TFBGA -54B
TFBGA -54B
TFBGA -54B
TFBGA -54B
TFBGA -54B
Grade
Commercial
Commercial
Extend temp
Extend temp
Special request
Special request
Pb
Free
Free
Free
Free
Pb
Pb
* EOREX reserves the right to change products or specification without notice.
Jul. 2006
1/17
www.eorex.com




EM488M1644VBB pdf, 반도체, 판매, 대치품
eorex
EM488M1644VBB
Absolute Maximum Rating
Symbol
Item
Rating
Units
VIN, VOUT
Input, Output Voltage
-0.3 ~ +4.6
V
VDD, VDDQ
Power Supply Voltage
-0.3 ~ +4.6
V
TOP Operating Temperature Range
Commercial
Extended
-0 ~ +70
-25 ~ +85
°C
TSTG
Storage Temperature Range
-55 ~ +150
°C
PD Power Dissipation
1W
IOS Short Circuit Current
50 mA
Note: Caution Exposing the device to stress above those listed in Absolute Maximum Ratings could
cause permanent damage. The device is not meant to be operated under conditions outside the
limits described in the operational section of this specification. Exposure to Absolute Maximum
Rating conditions for extended periods may affect device reliability.
Capacitance (VCC=3.3V, f=1MHz, TA=25°C)
Symbol
Parameter
Min. Typ. Max. Units
CCLK
CI
CO
Clock Capacitance
Input Capacitance for CLK, CKE, Address,
/CS, /RAS, /CAS, /WE, DQML, DQMU
Input/Output Capacitance
1.5
1.5
3.0
3.0 pF
3.0 pF
5.5 pF
Recommended DC Operating Conditions (TA= 0 ~+70; -25 ~ +85 °C)
Symbol
Parameter
VDD Power Supply Voltage
VDDQ
Power Supply Voltage (for I/O Buffer)
VIH Input Logic High Voltage
VIL Input Logic Low Voltage
Note: * All voltages referred to VSS.
* VIH (max.) = 5.6V for pulse width 3ns
* VIL (min.) = -2.0V for pulse width 3ns
Min.
2.75
2.75
2.0
-0.3
Typ. Max. Units
3.3 3.6 V
3.3 3.6 V
VDD+0.3
0.8
V
V
Jul. 2006
4/17
www.eorex.com

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EM488M1644VBB 전자부품, 판매, 대치품
eorex
AC Operating Test Conditions
(VDD=2.75V ~ 3.6V, TA=-10°C ~70°C; -25°C ~ +85°C)
Item
Output Reference Level
Output Load
Input Signal Level
Transition Time of Input Signals
Input Reference Level
EM488M1644VBB
Conditions
1.4V/1.4V
See diagram as below
2.4V/0.4V
2ns
1.4V
AC Operating Test Characteristics
(VDD=2.75V ~ 3.6V, TA=-10°C ~70°C; -25°C ~ +85°C)
Symbol
Parameter
-7 -7.5
Units
Min. Max. Min. Max.
tCK Clock Cycle Time
CL=3 7
CL=2 7.5
7.5
10
ns
tAC Access Time form CLK
CL=3
CL=2
5.4
5.4
5.4
ns
6
tCH CLK High Level Width
2.5 2.5
ns
tCL CLK Low Level Width
2.5 2.5
ns
CL=3 3
3
tOH Data-out Hold Time
CL=2 2
2
ns
tHZ
Data-out High Impedance
Time (Note 5)
CL=3
CL=2
3
7
3
7
ns
tLZ Data-out Low Impedance Time
0
0
ns
tIH Input Hold Time
0.8 1
ns
tIS Input Setup Time
1.5 1.5
ns
* All voltages referenced to VSS.
Note 5: tHZ defines the time at which the output achieve the open circuit condition and is not referenced to
output voltage levels.
Jul. 2006
7/17
www.eorex.com

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