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PDF CD4502BMS Data sheet ( Hoja de datos )

Número de pieza CD4502BMS
Descripción CMOS Strobed Hex Inverter/Buffer
Fabricantes Intersil Corporation 
Logotipo Intersil Corporation Logotipo



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CD4502BMS
December 1992
CMOS Strobed Hex Inverter/Buffer
Features
Pinout
• High Voltage Type (20V Rating)
• 2 TTL Load Output Drive Capability
CD4502BMS
TOP VIEW
• 3 State Outputs
• Common Output Disable Control
• Inhibit Control
• 100% Tested for Quiescent Current at 20V
• 5V, 10V and 15V Parametric Ratings
• Maximum Input Current of 1µA at 18V Over Full Pack-
age Temperature Range; 100nA at 18V and +25oC
• Noise Margin (Over Full Package/Temperature Range)
- 1V at VDD = 5V
- 2V at VDD = 10V
- 2.5V at VDD = 15V
D3 1
Q3 2
D1 3
3 STATE
OUTPUT DISABLE
4
Q1 5
D2 6
Q2 7
VSS 8
16 VDD
15 D6
14 Q6
13 D5
12 INHIBIT
11 Q5
10 D4
9 Q4
• Meets All Requirements of JEDEC Tentative Standard
No. 13B, “Standard Specifications for Description of
‘B’ Series CMOS Devices”
Applications
Functional Diagram
• 3 State Hex Inverter for Interfacing ICs with Data
Buses
• COS/MOS to TTL Hex Buffer
Description
CD4502BMS consists of six inverter/buffers with 3 state
outputs. A logic “1” on the OUTPUT DISABLE input
produces a high impedance state in all six outputs. This
feature permits common busing of the outputs, thus
simplifying system design. A Logic “1” on the INHIBIT input
switches all six outputs to logic “0” if the OUTPUT DISABLE
input is a logic “0”. This device is capable of driving two
standard TTL loads, which is equivalent to six times the
JEDEC “B” series IOL standard.
3 STATE 4
OUTPUT DISABLE
INHIBIT 12
D1 3
D2 6
D3 1
D4 10
D5 13
D6 15
5 Q1
7 Q2
2 Q3
9 Q4
11 Q5
14 Q6
The CD4502BMS is supplied in these 16-lead outline packages:
Braze Seal DIP
Frit Seal DIP
Ceramic Flatpack
H4T
H1F
H6W
VDD = 16
VSS = 8
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
7-473
File Number 3334

1 page




CD4502BMS pdf
Specifications CD4502BMS
TABLE 4. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS
LIMITS
PARAMETER
Supply Current
N Threshold Voltage
N Threshold Voltage
Delta
P Threshold Voltage
P Threshold Voltage
Delta
Functional
Propagation Delay Time
SYMBOL
CONDITIONS
IDD VDD = 20V, VIN = VDD or GND
VNTH VDD = 10V, ISS = -10µA
VTN VDD = 10V, ISS = -10µA
VTP
VTP
VSS = 0V, IDD = 10µA
VSS = 0V, IDD = 10µA
F
TPHL
TPLH
VDD = 18V, VIN = VDD or GND
VDD = 3V, VIN = VDD or GND
VDD = 5V
NOTES: 1. All voltages referenced to device GND.
2. CL = 50pF, RL = 200K, Input TR, TF < 20ns.
NOTES
1, 4
1, 4
1, 4
TEMPERATURE
+25oC
+25oC
+25oC
MIN
-
-2.8
-
1, 4
+25oC
0.2
1, 4
+25oC
-
1
1, 2, 3, 4
+25oC
+25oC
VOH >
VDD/2
-
3. See Table 2 for +25oC limit.
4. Read and Record
MAX
7.5
-0.2
±1
2.8
±1
VOL <
VDD/2
1.35 x
+25oC
Limit
UNITS
µA
V
V
V
V
V
ns
TABLE 5. BURN-IN AND LIFE TEST DELTA PARAMETERS +25oC
PARAMETER
SYMBOL
DELTA LIMIT
Supply Current - MSI-1
Output Current (Sink)
Output Current (Source)
IDD
IOL5
IOH5A
± 0.2µA
± 20% x Pre-Test Reading
± 20% x Pre-Test Reading
TABLE 6. APPLICABLE SUBGROUPS
CONFORMANCE GROUP
MIL-STD-883
METHOD
GROUP A SUBGROUPS
Initial Test (Pre Burn-In)
100% 5004
1, 7, 9
Interim Test 1 (Post Burn-In)
100% 5004
1, 7, 9
Interim Test 2 (Post Burn-In)
100% 5004
1, 7, 9
PDA (Note 1)
100% 5004
1, 7, 9, Deltas
Interim Test 3 (Post Burn-In)
100% 5004
1, 7, 9
PDA (Note 1)
100% 5004
1, 7, 9, Deltas
Final Test
100% 5004
2, 3, 8A, 8B, 10, 11
Group A
Sample 5005
1, 2, 3, 7, 8A, 8B, 9, 10, 11
Group B
Subgroup B-5
Sample 5005
1, 2, 3, 7, 8A, 8B, 9, 10, 11, Deltas
Subgroup B-6
Sample 5005
1, 7, 9
Group D
Sample 5005
1, 2, 3, 8A, 8B, 9
NOTE: 1. 5% Parameteric, 3% Functional; Cumulative for Static 1 and 2.
CONFORMANCE GROUPS
Group E Subgroup 2
TABLE 7. TOTAL DOSE IRRADIATION
MIL-STD-883
METHOD
TEST
PRE-IRRAD
POST-IRRAD
5005
1, 7, 9
Table 4
READ AND RECORD
IDD, IOL5, IOH5A
IDD, IOL5, IOH5A
IDD, IOL5, IOH5A
IDD, IOL5, IOH5A
Subgroups 1, 2, 3, 9, 10, 11
Subgroups 1, 2 3
READ AND RECORD
PRE-IRRAD
POST-IRRAD
1, 9 Table 4
7-477

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