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PDF KSZ9031MNX Data sheet ( Hoja de datos )
| Número de pieza | KSZ9031MNX | |
| Descripción | Gigabit Ethernet Transceiver | |
| Fabricantes | Microchip | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de KSZ9031MNX (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
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KSZ9031MNX
Gigabit Ethernet Transceiver with GMII/MII
Support
Target Applications
• Laser/Network Printer
• Network Attached Storage (NAS)
• Network Server
• Broadband Gateway
• Gigabit SOHO/SMB Router
• IPTV
• IP Set-Top Box
• Game Console
• IP Camera
• Triple-Play (Data, Voice, Video) Media Center
• Media Converter
Features
• Single-Chip 10/100/1000 Mbps Ethernet Trans-
ceiver Suitable for IEEE 802.3 Applications
• GMII/MII Standard Interface with 3.3V/2.5V/1.8V
Tolerant I/Os
• Auto-Negotiation to Automatically Select the
Highest Link-Up Speed (10/100/1000 Mbps) and
Duplex (Half/Full)
• On-Chip Termination Resistors for the Differential
Pairs
• On-Chip LDO Controller to Support Single 3.3V
Supply Operation
• Jumbo Frame Support Up to 16 KB
• 125 MHz Reference Clock Output
• Energy-Detect Power-Down Mode for Reduced
Power Consumption When the Cable is Not
Attached
• Wake-On-LAN (WOL) Support with Robust Cus-
tom-Packet Detection
• Programmable LED Outputs for Link, Activity, and
Speed
• Baseline Wander Correction
• LinkMD TDR-based Cable Diagnostic to Identify
Faulty Copper Cabling
• Parametric NAND Tree Support to Detect Faults
Between Chip I/Os and Board
• Loopback Modes for Diagnostics
• Automatic MDI/MDI-X Crossover to Detect and
Correct Pair Swap at All Speeds of Operation
• Automatic Detection and Correction of Pair
Swaps, Pair Skew, and Pair Polarity
• MDC/MDIO Management Interface for PHY Reg-
ister Configuration
• Interrupt Pin Option
• Power-Down and Power-Saving Modes
• Operating Voltages
- Core (DVDDL, AVDDL, AVDDL_PLL): 1.2V
(External FET or Regulator)
- VDD I/O (DVDDH): 3.3V, 2.5V, or 1.8V
- Transceiver (AVDDH): 3.3V or 2.5V
(Commercial Temp.)
• 64-pin QFN (8 mm × 8 mm) Package
2016 Microchip Technology Inc.
DS00002096C-page 1
1 page  
2.0 PIN DESCRIPTION AND CONFIGURATION
FIGURE 2-1:
64-QFN PIN ASSIGNMENT (TOP VIEW)
KSZ9031MNX
AVDDH 1
TXRXP_A 2
TXRXM_A 3
AVDDL 4
AVDDL 5
NC 6
TXRXP_B 7
TXRXM_B 8
AGNDH 9
TXRXP_C 10
TXRXM_C 11
AVDDL 12
AVDDL 13
TXRXP_D 14
TXRXM_D 15
AVDDH 16
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
KSZ9031MNX
PADDLE GROUND
(ON BOTTOM OF CHIP)
48
RX_CLK /
PHYAD2
47 RX_ER
46 DVDDH
45
RX_DV /
CLK125_EN
44
RXD0/
MODE0
43
RXD1/
MODE1
42 DVDDL
41
RXD2/
MODE2
40 DVDDH
39
RXD3/
MODE3
38 RXD4
37 RXD5
36 DVDDL
35 RXD6
34 RXD7
33 TX_EN
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
2016 Microchip Technology Inc.
DS00002096C-page 5
5 Page 
KSZ9031MNX
TABLE 2-1: SIGNALS - KSZ9031MNX (CONTINUED)
Pin
Number
Pin
Name
Type
Note
2-1
Description
125 MHz clock output
This pin provides a 125 MHz reference clock output option for use by the
55
CLK125_NDO/
LED_MODE
I/O
MAC.
Config mode: The voltage on this pin is sampled during the power-up/reset
process to determine the value of LED_MODE. See the Strapping Options -
KSZ9031MNX section for details.
Chip reset (active low)
56
RESET_N
Ipu
Hardware pin configurations are strapped-in (sampled and latched) at the de-
assertion (rising edge) of RESET_N. See the Strapping Options -
KSZ9031MNX section for details.
57
TX_CLK
O MII mode: MII TX_CLK (Transmit Reference Clock) output
On-chip 1.2V LDO controller output
58
LDO_O
O
This pin drives the input gate of a P-channel MOSFET to generate 1.2V for
the chip’s core voltages. If the system provides 1.2V and this pin is not used,
it can be left floating.
59
AVDDL_PLL
P 1.2V analog VDD for PLL
25 MHz crystal feedback
60
XO
O
This pin connects to one end of an external 25 MHz crystal.
This pin is a no connect if an oscillator or other external (non-crystal) clock
source is used.
Crystal/Oscillator/External Clock input
61
XI
I
This pin connects to one end of an external 25 MHz crystal or to the output of
an oscillator or other external (non-crystal) clock source.
25 MHz ±50 ppm tolerance
No connect
62 NC — This pin is not bonded and can be connected to AVDDH power for footprint
compatibility with the KSZ9021GN Gigabit PHY.
63
ISET
I/O
Set the transmit output level.
Connect a 12.1 kΩ 1% resistor to ground on this pin.
64
AGNDH
GND Analog ground.
Paddle
Note 2-1
P_GND
GND Exposed paddle on bottom of chip.
Connect P_GND to ground.
P = power supply
GND = ground
I = input
O = output
I/O = bi-directional
Ipu = Input with internal pull-up (see Electrical Characteristics for value).
Ipu/O = Input with internal pull-up (see Electrical Characteristics for value) during power-up/reset;
output pin otherwise.
2016 Microchip Technology Inc.
DS00002096C-page 11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet KSZ9031MNX.PDF ] | |
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