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TC55257CFTL-10L PDF 데이터시트 : 부품 기능 및 핀배열

부품번호 TC55257CFTL-10L
기능 SILICON GATE CMOS STATIC RAM
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TC55257CFTL-10L 데이터시트, 핀배열, 회로
TOSHIBA
TC55257CPL/CFL/CSPL/CFIL/CTRL-70L/85L/10L
SILICON GATE CMOS
PRELIMINARY
32,768 WORD x 8 BIT STATIC RAM
Description
The TC55257CPL is a 262,144 bit CMOS static random access memory organized as 32,768 words by 8 bits and operated from
a single 5V power supply. Advanced circuit techniques provide both high speed and low power features with an operating current of
5mNMHz (typ.) and a minimum cycle time of 70ns.
When CE is a logical high, the device is placed in a low power standby mode in which the standby current is 21lA at room tem-
perature. The TC55257CPL has two control inputs. Chip enable (CE) allows for device selection and data retention control, while
an output enable input (OE) provides fast memory access. The TC55257CPL is suitable for use in microprocessor systems where
high speed, low power, and battery backup are required.
The TC55257CPL is offered in a standard dual-in-line 28-pin plastic package (0.6/0.3 inch width), a small outline plastic pack-
age, and a thin small outline plastic package (forward type, reverse type).
Features
• Low power dissipation:
• Standby current:
• Single 5V power supply
• Access time (max.)
27.5mW/MHz (typ.)
21lA (max.) at Ta = 25°C
TC55257CPL/CFL/CSPL/CFTL/CTRL
Access Time
CE Access Time
OE Access Time
-70L
70ns
70ns
35ns
-85L
85ns
85ns
45ns
-10L
100ns
100ns
Sans
• Power down feature:
CE
• Data retention supply voltage:
2.0 - 5.5V
• Inputs and outputs TIL compatible
• Package
TC55257CPL: DIP28-P-600
TC55257CFL
TC55257CSPL
TC55257CFTL
TC55257CTRL
: SOP28-P-450
: DIP28-P-300B
: TSOP28-P
: TSOP28-P-A
Pin Names
AO - A14 Address Inputs
RIW
ReadIWrite Control Input
OE Output Enable Input
CE Chip Enable Input
1/01 - 1/08 Data Input/Output
Voo
GND
Power (+5V)
Ground
Pin Connection (Top View)
o 28 PIN DIP & SOP
o 28 PIN TSOP
A14
A12
A7
AS
A4
A3
A2
1t0l
1/02
1/03
GND
(for.vard type)
voo
RIW
All ~4
A8
A9
All
OE
Al0
CE
1108
1107
1/06
1/05
1/04
28
(reverse type)
1~
28 1~
PIN NO.
PIN NAME
PIN NO.
PIN NAME
12
OE A11
15 16
A2 A1
3 4 5 6 7 8 9 10 11 12 13 14
Ag
A8 A13 RIW Voo A14 A12
A7
As
A5
A4
A3
17 18 19 20 21 22 23 24 25 26 27 28
Ao 1/01 1/02 1/03 GND 1/04 1/05 1/06 1/07 1/08 CE A10
TOSHIBA AMERICA ELECTRONIC COMPONENTS. INC.
A-59




TC55257CFTL-10L pdf, 반도체, 판매, 대치품
TC55257CPUCFUCSPUCFTUCTRL-70U85U10L Static RAM
= =AC Characteristics (Ta 0 - 70°C, Voo SV±10% )
Read Cycle
SYMBOL
PARAMETER
tRC
tAcc
tco
tOE
tCOE
tOEE
too
tooo
tOH
Read Cycle Time
Address Access Time
CE Access Time
Output Enable to Output in Valid
Chip Enable (CE) to Output in Low-Z
Output Enable to Output in Low-Z
Chip Enable (CE) to Output in High-Z
Output Enable to Output in High-Z
Output Data Hold Time
TC55257CPL/CFL/CSPL/CFTL/CTRL
·70L ·85L ·10L
MIN. MAX. MIN. MAX. MIN. MAX.
70 - 85 - 100 -
- 70 - 85 - 100
- 70 - 85 - 100
- 35 - 45 - 50
10 -
10 -
10 -
5-
5-
5-
- 25 - 30 - 50
- 25 - 30 - 40
10 -
10 -
10 -
UNIT
ns
Write Cycle
SYMBOL
PARAMETER
twc
twp
tcw
tAS
tWR
toow
tOEW
tos
tOH
Write Cycle Time
Write Pulse Width
Chip Selection to End of Write
Address Setup Time
Write Recovery Time
RIW to Output in High-Z
RIW to Output in Low-Z
Data Setup Time
Data Hold Time
AC Test Conditions
Input Pulse Levels
Input Pulse Rise and Fall Time
Input Timing Measurement Reference Levels
Output Timing Measurement Reference Levels
Output Load
TC55257CPL/CFL/CSPL/CFTL/CTRL
-70L -85L ·10L
MIN. MAX. MIN. MAX. MIN. MAX.
70 - 85 - 100 -
50 - 60 - 70 -
60 - 65 - 90 -
0-
0-
0-
0-
0-
0-
- 25 - 30 - 50
5-
5-
5-
30 - 40 - 40 -
0-
0-
0-
UNIT
ns
2.4V/0.6V
5ns
1.5V
1.5V
1 TTL Gate and CL = 1OOpF
A-62
TOSHIBA AMERICA ELECTRONIC COMPONENTS, ·INC.
PRELIMINARY

4페이지










TC55257CFTL-10L 전자부품, 판매, 대치품
Static RAM TC55257CPUCFUCSPUCFTUCTRL-70U85U10L
Data Retention Characteristics (Ta =0 - 70°C)
SYMBOL
PARAMETER
VOH
IOOS2
tCOR
tR
Data Retention Supply Voltage
Standby Current
Chip Deselect to Data Retention Mode
Recovery Time
I VOH =3.OV
IVOH =5.5V
MIN.
2.0
-
-
0
tRC(1)
TYP.
-
-
-
-
-
MAX.
5.5
10*
20
-
-
UNIT
V
IJA
ns
Note (1): Read Cycle Time
*21JA (max.) Ta == 0 - 40°C
CE Controlled Data Retention Mode
DATA RETENTION MODE
Voo-O.2V
GND
Note (2): If the V1H of CE is 2.2V in operation, IDDS1 current flows during the period that the VDD voltage is going down from 4.5V to 2.4Y.
PRELIMINARY
TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC.
A-65

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TC55257CFTL-10

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TC55257CFTL-10L

SILICON GATE CMOS STATIC RAM

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