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PEEL16V8-25 데이터시트 PDF




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부품번호 PEEL16V8-25 기능
기능 CMOS Programmable Electrically Erasable Logic
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PEEL16V8-25 데이터시트, 핀배열, 회로
Features
PEEL™ 16CV8 -25
CMOS Programmable Electrically Erasable Logic Device
Compatible with Popular 16V8 Devices
- 16V8 socket and function compatible
- Programs with standard 16V8 JEDEC file
- 20-pin DIP, SOIC, TSSOP, and PLCC
CMOS Electrically Erasable Technology
- Superior factory testing
- Reprogrammable in plastic package
- Reduces retrofit and development costs
Application Versatility
- Replaces random logic
- Super sets standard 20-pin PLDs (PALs)
General Description
The PEELTM 16CV8 is a Programmable Electrically Erasable Logic
(PEEL) device providing an attractive alternative to ordinary PLDs. The
PEELTM 16CV8 offers the performance, flexibility, ease of design and
production practicality needed by logic designers today.
The PEELTM 16CV8 is available in 20-pin DIP, PLCC, SOIC and TSSOP
packages (see Figure 1) with 25ns speed and power consumption as low
as 37mA. EE-Reprogrammability provides the convenience of instant
reprogramming for development and reusable production inven- tory
minimizing the impact of programming changes or errors. EE-
Reprogrammability also improves factory testability, thus assuring the
highest quality possible.
Multiple Speed, Power Options
- Speeds range 25ns
- Power as low as 37mA @ 25mHZ
Development / Programmer Support
- Third party software and programmers
- Anachip WinPLACE Development Software
- Automatic programmer translation and JEDEC file translation
software available for the most popular PAL devices
The PEELTM 16CV8 architecture allows it to replace over standard 20-
pin PLDs (PAL, GAL, EPLD etc.). See Figure 2. Anachip’s PEELTM
16CV8 can be programmed with existing 16CV8 JEDEC file. Some pro-
grammers also allow the PEELTM 16CV8 to be programmed directly
from PLD 16L8, 16R4, 16R6 and 16R8 JEDEC files. Additional develop-
ment and programming support for the PEELTM16CV8 is provided by
popular third-party programmers and development software. Anachip
also offers free WinPLACE development software.
Figure 1 - Pin Configuration
Figure 2 - Block Diagram
This datasheet contains new product information. Anachip Corp. reserves the rights to modify the product specification without notice. No liability is assumed as a result of the use of this product. No rights under
any patent accompany the sale of the product.
Rev. 1.0 Dec 16, 2004
1/11




PEEL16V8-25 pdf, 반도체, 판매, 대치품
Complex Mode
In Complex mode, seven product terms feed the OR array which can
generate a purely combinatorial function for the output pin. The pro-
grammable output polarity selector provides active-high or active-low
logic, eliminating the need for external inverters. The output buffer is
controlled by the eighth product term, allowing the macrocell to be con-
figured for input, output, or bidirectional functions. Feedback into the
array for input or bidirectional functions is available on all pins except 12
and 19. Figure 4 shows the possible complex mode macrocell configura-
tions.
1 Registered Mode
Active Low Registered Output
OE PIN
CLK PIN
DQ
Q
2 Registered Mode
Active High Registered Output
OE PIN
CLK PIN
DQ
Q
3 Registered Mode
Active Low Combinatorial Output
PRODUCT TERM
4 Registered Mode
Active High Combinatorial Output
PRODUCT TERM
1 Complex Mode
Active Low Output
PRODUCT TERM
2 Complex Mode
Active High Output
PRODUCT TERM
FPiEgEurLeTM4
- Macrocell
16CV8 (see
Configurations for
Figure 7 for Logic
the Complex
Array)
Mode
of
the
Registered Mode
Registered mode provides eight product terms to the OR array for regis-
tered functions. The programmable output polarity selector provides
active-high or active-low logic, eliminating the need for external invert-
ers. (Note, however, that if register is selected, the PEELTM 16CV8 reg-
gisters power-up reset and so before the first clock arrives the output at
the pin will be low if the user has selected active-high logic and high if the
user has selected active-low logic. If combinatorial is selected, the output
will be a function of the logic.) For registered functions, the output buffer
enable is controlled directly from the /OE control pin. Feedback into the
array comes from the macrocell register. In Registered mode, input pins
1 and 11 are permanently allocated as CLK and /OE, respec- tively. Figure
8 shows the logic array of the PEELTM 16CV8 configured in Registered
mode.
Registered mode also provides the option of configuring a macrocell for
combinatorial operation, with seven product terms feeding the OR func-
tion.
Again the programmable output polarity selector provides active-high or
active-low logic. The output buffer enable is controlled by the eighth
product term, allowing the macrocell to be configured for input, output, or
bidirectional functions. Feedback into the array for input or bidirectional
functions is available on all I/O pins. Macrocell Configurations for the
Registered Mode of the PEELTM 16CV8
Figure 5 - Macrocell Configurations for the Registered Mode of the
PEELTM 16CV8 (see Figure 8 for logic Array)
Design Security
The PEELTM 16CV8 provides a special EEPROM security bit that pre-
vents unauthorized reading or copying of designs programmed into the
device. The security bit is set by the PLD programmer, either at the con-
clusion of the programming cycle or as a separate step, after the device
has been programmed. Once the security bit has been set it is impossi-
ble to verify (read) or program the PEELTM until the entire device has first
been erased with the bulk-erase function.
Signature Word
The signature word feature allows a 64-bit code to be programmed into
the PEELTM 16CV8. The code cannot be read back after the security bit
has been set. The signature word can be used to identify the pattern
programmed into the device or to record the design revision, etc.
Anachip Corp.
www.anachip.com.tw
4/11
Rev. 1.0 Dec 16, 2004

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PEEL16V8-25 전자부품, 판매, 대치품
CLK 1
I2
I3
I4
I5
I6
I7
I8
I9
Figure 8 - PEEL TM 16CV8 Logic Array - Registered Mode (see Figure 5 for macrocell details)
Anachip Corp.
www.anachip.com.tw
7/11
MACRO
CELL
19 I/O
MACRO
CELL
18 I/O
MACRO
CELL
17 I/O
MACRO
CELL
16 I/O
MACRO
CELL
15 I/O
MACRO
CELL
14 I/O
MACRO
CELL
13 I/O
MACRO
CELL
12 I/O
11 OE
Rev. 1.0 Dec 16, 2004

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