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ADF41020 PDF 데이터시트 ( Data , Function )

부품번호 ADF41020 기능
기능 18 GHz Microwave PLL Synthesizer
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ADF41020 데이터시트, 핀배열, 회로
Data Sheet
18 GHz Microwave PLL Synthesizer
ADF41020
FEATURES
18 GHz maximum RF input frequency
Integrated SiGe prescaler
Software compatible with the ADF4106/ADF4107/ADF4108
family of PLLs
2.85 V to 3.15 V PLL power supply
Programmable dual-modulus prescaler
8/9, 16/17, 32/33, 64/65
Programmable charge pump currents
3-wire serial interface
Analog and digital lock detect
Hardware and software power-down mode
4000 V HBM/1500 V CDM ESD performance
APPLICATIONS
Microwave point-to-point/multipoint radios
Wireless infrastructure
VSAT radios
Test equipment
Instrumentation
GENERAL DESCRIPTION
The ADF41020 frequency synthesizer can be used to implement
local oscillators as high as 18 GHz in the up conversion and
down conversion sections of wireless receivers and transmitters.
It consists of a low noise, digital phase frequency detector
(PFD), a precision charge pump, a programmable reference
divider, and high frequency programmable feedback dividers
(A, B, and P). A complete phase-locked loop (PLL) can be
implemented if the synthesizer is used with an external loop
filter and voltage controlled oscillator (VCO). The synthesizer
can be used to drive external microwave VCOs via an active
loop filter. Its very high bandwidth means a frequency doubler
stage can be eliminated, simplifying system architecture and
reducing cost. The ADF41020 is software-compatible with the
existing ADF4106/ADF4107/ADF4108 family of devices from
Analog Devices, Inc. Their pinouts match very closely with
the exception of the ADF41020’s single-ended RF input pin,
meaning only a minor layout change is required when updating
current designs.
REFIN
AVDD DVDD
FUNCTIONAL BLOCK DIAGRAM
VP GND
R COUNTER
PHASE
FREQUENCY
DETECTOR
REFERENCE
RSET
CHARGE
PUMP
CP
CLK
DATA
LE
24-BIT INPUT
REGISTER
R COUNTER
LATCH
FUNCTION
LATCH
A, B COUNTER
LATCH
RFIN
3pF
50Ω
N = 4(BP + A)
DIVIDE
BY 4
P/P+ 1
A AND B
COUNTERS
LOCK
DETECT
CURRENT
SETTING 1
CURRENT
SETTING 2
CPI3 CPI2 CPI1 CPI6 CPI5 CPI4
AVDD
SDOUT
MUX
HIGH-Z
MUXOUT
M3 M2 M1
ADF41020
GND
CE
GND
Figure 1.
Rev. B
Document Feedback
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rights of third parties that may result from its use. Specifications subject to change without notice. No
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One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2012–2014 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com




ADF41020 pdf, 반도체, 판매, 대치품
ADF41020
Data Sheet
Parameter
NOISE CHARACTERISTICS
Normalized Phase Noise Floor4
Normalized 1/f Noise5
Phase Noise Performance6
5.7 GHz
12.5 GHz7
17.64 GHz
Spurious Signals
5.7 GHz
12.5 GHz7
17.64 GHz
Min
Typ
Max Unit
Test Conditions/Comments
−221
−118
−89
−82
−96
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
PLL loop bandwidth = 500 kHz
Normalized to 10 kHz offset at 1 GHz
At VCO output
At 1 kHz offset and 2.5 MHz PFD frequency with
20 kHz loop bandwidth
At 3 kHz offset and 2.5 MHz PFD frequency with
20 kHz loop bandwidth
At 100 kHz offset and 90 MHz PFD frequency with
700 kHz loop bandwidth
−80/−86
−98/<−110
−109/−113
dBc At 2.5 MHz/5 MHz and 2.5 MHz PFD frequency
dBc At 2.5 MHz/5 MHz and 2.5 MHz PFD frequency
dBc At 90 MHz/180 MHz and 90 MHz PFD frequency
1 This is the maximum operating frequency of the CMOS counters. The prescaler value should be chosen to ensure that the RF input is divided down to a frequency that
is less than this value.
2 Guaranteed by design. Sample tested to ensure compliance.
3 TA = 25°C; AVDD = DVDD = VP = 3.0 V; P = 16; fREFIN = 100 MHz; fPFD = 100 MHz; RFIN = 12.8 GHz.
4 The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20 log N (where N is the N divider
value) and 10 log fPFD. PNSYNTH = PNTOT − 10 log fPFD − 20 log N.
5 The PLL phase noise is composed of 1/f (flicker) noise plus the normalized PLL noise floor. The formula for calculating the 1/f noise contribution at an RF frequency, fRF,
and at a frequency offset, f, is given by PN = PN1_f + 10 log(10 kHz/f) + 20 log(fRF/1 GHz). Both the normalized phase noise floor and flicker noise are modeled in
ADIsimPLL.
6 The phase noise is measured with a Rohde & Schwarz FSUP spectrum analyzer. The reference is provided by a Rohde & Schwarz SMA100A.
7 The phase noise and spurious noise is measured with the EV-ADF41020EB1Z evaluation board and the Rohde & Schwarz FSUP spectrum analyzer.
TIMING CHARACTERISTICS
AVDD = DVDD = VP = 3.0 V, GND = 0 V, RSET = 5.1 kΩ, dBm referred to 50 Ω, TA = TMAX to TMIN, unless otherwise noted.
Table 2.
Parameter
t1
t2
t3
t4
t5
t6
Limit
10
10
25
25
10
20
Unit
ns min
ns min
ns min
ns min
ns min
ns min
Test Conditions/Comments
DATA to CLK setup time
DATA to CLK hold time
CLK high duration
CLK low duration
CLK to LE setup time
LE pulse width
t3 t4
CLK
DATA DB23 (MSB)
LE
LE
t1 t2
DB22
DB2
DB1 (CONTROL
BIT C2)
Figure 2. Timing Diagram
DB0 (LSB)
(CONTROL BIT C1)
t6
t5
Rev. B | Page 4 of 16

4페이지










ADF41020 전자부품, 판매, 대치품
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
20
10 8/9 PRESCALER
0
–10
–20
–30
–40
16/17 PRESCALER
–50
–60
–70
0
5 10 15
FREQUENCY (GHz)
Figure 4. RF Input Sensitivity
20
25
6
5 5.0mA
4.375mA
4 3.75mA
3.125mA
3 2.5mA
2 1.875mA
1.25mA
1 0.625mA
0 0.625mA
–1 1.25mA
1.875mA
–2 2.5mA
–3 3.125mA
3.75mA
–4 4.375mA
–5 5.0mA
–6
0 0.5 1.0 1.5 2.0 2.5
VCP (V)
Figure 5. Charge Pump Output Characteristics
3.0
0
–20
–40
–60
–80
–100
–120
–140
–160
–180
1k
10k 100k 1M 10M
FREQUENCY OFFSET (Hz)
Figure 6. Closed-Loop Phase Noise, RF = 12.5 GHz, PFD = 2.5 MHz,
Loop Bandwidth = 20 kHz
ADF41020
10
5
0
–5
–10
–15
–20
–25
0
100 200 300 400 500 600 700 800 900 1000
FREQUENCY (MHz)
Figure 7. REFIN Sensitivity
FREQ UNIT: GHz KEYWORD: R
PARAM TYPE: s
DATA FORMAT: MA
FREQ
4.0
4.2
4.4
4.6
4.8
5.0
5.2
5.4
5.6
5.8
6.0
6.2
6.4
6.6
6.8
7.0
7.2
7.4
7.6
7.8
8.0
8.2
8.4
8.6
8.8
9.0
9.2
9.4
9.6
9.8
10.0
MAGS11
0.20099200
0.19669930
0.19140480
0.18317790
0.17232760
0.16071930
0.14943970
0.13791310
0.12839340
0.12090700
0.11516160
0.11252430
0.11213720
0.11236920
0.11323590
0.11401910
0.11361600
0.11225360
0.10909150
0.10484100
0.09871251
0.09258573
0.08667851
0.08075383
0.07542522
0.07048169
0.06751262
0.06561201
0.06308079
0.05995205
0.05666475
ANGS11
–133.9429000
–134.7069000
–135.0024000
–135.1249000
–135.0415000
–135.1840000
–136.0447000
–137.7694000
–140.5623000
–144.7454000
–149.8260000
–155.1801000
–160.0477000
–164.5794000
–168.1217000
–170.9163000
–173.2882000
–175.2539000
–176.9327000
–179.0774000
178.5525000
175.9697000
172.5878000
168.3692000
163.5676000
159.0954000
154.6976000
149.2087000
142.2284000
137.8226000
134.1730000
FREQ
10.2
10.4
10.6
10.8
11.0
11.4
11.8
12.2
12.6
13.0
13.4
13.8
14.2
14.6
15.0
15.2
15.4
15.6
15.8
16.0
16.2
16.4
16.6
16.8
17.0
17.2
17.4
17.6
17.8
18.0
MAGS11
0.05542031
0.05306026
0.05123230
0.04471957
0.03846882
0.03402513
0.04456061
0.05158395
0.06039219
0.05580344
0.08402054
0.10374910
0.11639920
0.13647950
0.16700580
0.18309070
0.19458010
0.20377790
0.21170140
0.21883690
0.22280700
0.22498210
0.22589250
0.22572100
0.22596830
0.23197900
0.24339450
0.26023130
0.28636130
0.31905490
ANGS11
130.0581000
126.9556000
115.8988000
102.0333000
86.3895600
51.1515300
21.0829700
16.8124600
16.5178200
31.4631600
36.3540700
18.8428500
0.2817307
–15.4473000
–22.3273100
–24.3333900
–25.3870800
–25.0101800
–24.2554800
–23.4312200
–23.5596400
–24.411100
–26.5202700
–30.3773300
–36.2808700
–42.8398200
–50.7222200
–57.5844600
–63.0764200
–67.5389600
Figure 8. S-Parameters
Rev. B | Page 7 of 16

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부품번호상세설명 및 기능제조사
ADF41020

18 GHz Microwave PLL Synthesizer

Analog Devices
Analog Devices

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