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CDP68HC05D2 데이터시트, 핀배열, 회로
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ 6805-Serles Microprocessors and Microcomputers
CDP68HC05D2
HCMOS Microcomputer
Introduction
General
The CDP68HC05D2 Microcomputer Unit (MCU) belongs to
the CDP6805 Family of Microcomputers This 8-bit MCU
contains on-chip oscillator CPU, RAM, ROM, 1/0, and
Timer The fully static design allows operation at frequen-
cies down to DC, further reducing its already low-power
consumption. It is a low-power processor designed for low-
end to mid-range applications in the telecommunications,
consumer, automotive, and industrial markets where very
low power consumption constitutes an Important factor.
The CDP68HC05D2 is supplied in a 40-lead hermetic dual-
in-line side brazed ceramic package (0 suffix), a 40-lead
dual-in-line plastic package (E suffix), and a 44-lead Plastic
Chip Carner (Q suffix).
Specific Features
• Typical power:
Operating, 25 mW
WAIT,7.5mW
STOP,5p.W
Fully static operation
96 bytes of on-chip RAM
2176 bytes of on-chip ROM
31110 lines
12 programmable open-dram output lines
On-chip oscillator for Timer
2.1 MHz internal operating frequency
Internal 16-bit timer
Serial Peripheral Interface (SPI)
External (~), timer, Port B, and Serial Interrupts
Self check mode
Single 2.5 to 6 volt supply (2-V data retention mode)
RC or crystal on-chip OSCillator
8x8 multiply Instruction
True bit manipulation
Indexed addreSSing for tables
Memory mapped 110
Functional Pin Descriptions
Voo and Vss
Power is supplied to the MCU using these two pins Vee is
power and V•• is ground.
N.C.
The pin labelled N.C. should be left disconnected.
III
IRQ (Maskable Interrupt Request)
IRQ IS a programmable option which provides two different
chOices of interrupt triggering sensitivity. These options
are. 1) negative edge-sensitive triggering only, or 2) both
negative edge-sensitive and level-sensitive triggering. In
the latter case, either type of input to the IRQ pin will pro-
duce the interrupt. The MCU completes the current instruc-
tion before it responds to the interrupt request. When the
IRQ pin goes low for at least onet'LlH, a logic one is latched
internally to Signify that an interrupt has been requested.
When the MCU completes its current instruction, the inter-
rupt latch is tested. If the interrupt latch contains a logic
one, and the interrupt mask bit (I bit) in the condition code
register is clear, the MCU then begins the interrupt se-
quence. If the option is selected to include level-sensitive
triggering, then the IRQ input requires an external resistor
to Vee for "wire-OR" operation. See the INTERRUPTS sec-
tion for more detail.
RESET
The RESET input IS not required for startup but can be used
to reset the MCU internal state and provide an orderly soft-
ware startup procedure. Refer to the RESETs section for a
detailed description
TSM-204A
________________________________________________________________________________ 193




CDP68HC05D2 pdf, 반도체, 판매, 대치품
680S-Serles Microprocessors and Microcomputers _ _ _ _ _ _ _ _ _ _ _ _ _ __
CDP68HC05D2
PBO-PB7
These eight lines comprise port S. The state of any pin IS
software programmable and all port S lines are configured
as Input during power-on or reset. These lines may be
configured to generate interrupts. Refer to port S interrupt
section. Refer to INPUT/OUTPUT PROGRAMMING par-
agraph below for a detailed description of I/O program-
ming
PCO-PC7
These eight lines comprise port C. The state of any pin is
software programmable and all port C lines are configured
as Input during power-on or reset. Refer to INPUT/OUT-
PUT PROGRAMMING paragraph below for a detailed de-
scription of I/O programming.
PDO-POS, PD7
These seven lines comprise Port D. Four PinS (PD2-PD5)
are individually programmable as either inputs or outputs.
PD7 is always an input line. PDO-PD5Iines are set as inputs
on power-on or reset. The enabled Timer and SPI special
functions listed below affect the pins on this port. PDO-PD1
(referred to as TOSC1, TOSC2) are used to control the
oscillator for the timer in the external clock mode. If the
external clock mode is not used, these pinS are configured
as inputs only. See sections EXTERNAL TIMER OSCILLA-
TOR and SPECIAL PURPOSE PORT. MOSI is the SPI Serial
Data Output (in Master Mode) MISO is the SPI Serial Data
Input (In Master Mode). SCK is the clock for the SPI (con-
figured as output in the Master Mode). SS is the Slave Select
Input for the SPI.
Note: It is recommended that all unused inputs (except OSC2) and
1/0 ports configured as inputs be tied to an appropriate logic level
(e.g. either Vee or Vss).
Parallel I/O
The I/O register section is found in the first 32 bytes of
memory and Includes the following.
• Three programmable parallel ports (Ports A, S, and C) .
• One port (Port D) With three input lines and four pro-
grammable lines which share its external pins with Serial
Peripheral Interface (SPI) and Timer functions.
The general memory arrangement for each system has a
control register, followed by a status register, followed by a
data register. A CPU read of any undefined/unused bits will
obtain a value of "0". The register assignment may befound
in Table II.
Input/Output Programming
Parallel Ports
Ports A, S, and C may be programmed as an input or an
output under software control. The direction of the pins is
determined by the state of the corresponding bit in the port
data direction register (DDR). Each 8-bit port has an asso-
ciated 8-bit data direction register. Any port A, port S, or
port C pin is configured as an output if its corresponding
DDR bit is set to a logic one. A pin is configured asan input if
its corresponding DDR bit is cleared to a logic zero. At
power-on or reset all DDRs are cleared, which configure all
port A, S, and C pins as inputs. The data direction registers
are capable of being written to or read by the processor.
Refer to Fig. 3 and Table I. During the programmed output
state, a read of the data register actually reads the value of
the output data latch and not the I/O pin.
As an option for Port A, the eight Port A outputs (PAO-PA7)
can be programmed to be open drain outputs when bit 0 in
the Special Port Control/Status register is set and their DDR
bits are set. Also, the setting of the "Wired-OR" Mode
(WOM) bit In the SPI Control Registerwill cause Port 0 lines
2-5 (when programmed as outputs) to be open drain
SPECIAL PURPOSE PORT
Port 0 contains four individually programmable bi-direc-
tiona I lines (PD2-PD5) and three input lines (PDO, PD1, and
PD7). The direction of the four bi-directlonallines is deter-
mined by the state of the data direction register (DDR).
Each of these four lines has an associated DDR bit. The
validity of a port bit is determined by whether the SPI sys-
tem and external timer oscillator are enabled or disabled.
When the SPI system is disabled, lines PD2-PD5 behave as
normal 1/0 lines and the corresponding DDR bits determine
whether the lines are inputs or outputs. Lines PD~ and PD1
are Inputs when the external timer oscillator is not used.
However, once the external timer oscillator has been
enabled, PD1 will become an output-only line until the
processor is reset.
A write to bits 0, 1, 6, and 7 of the Port 0 Data Direction
Register will have no effect. A read of DDR bits 0,1,6, and 7
will always return zeros.
Note: When uSing the Senal Penpherallnterface (SPI), bit 5of Port
o is dedicated as the Slave Select (SS) Input when the SPI system IS
enabled In SPI Slave Mode, OOR bit 5 has no meaning oreftect In
SPI Master Mode, OOR bit 5 determines whether Port 0 bit 5 IS an
error detect Input to the SPI (OOR bit clear) or a general purpose
output line (OOR bit set)
For bits 2, 3, and 4 (MISO, MOSI, and SCK), If the SPI is
enabled and expects the bit to be an input, itwill bean input
regardless of the state of the DDR bit. If the SPI is enabled
and expects the bit to be an output, it will be an output ONLY
if the DDR bit is set.
Memory
The CDP68HC05D2 has a total address space of 8192 bytes.
The address map Is shown in Fig, 4. The CDP68HC05D2 has
implemented 2550 bytes of the address locations.
The first 256 bytes of memory (page zero) is comprised of
the I/O port locations, timer locations, 128 bytes of ROM
and 96 bytes of RAM. The next 2048 bytes comprise the user
ROM. The 16 highest address bytes contain the reset and
interrupt vectors.
The stack pOinter is used to address data stored on the
stack. Data is stored on the stack during interrupts and
subroutine calls. At power-up, the stack pointer is set to
$OOFF and it is decremented as data is pushed on the stack.
When data is removed from the stack, the stack pointer is
incremented. A maximum of64 bytes of RAM isavailablefor
stack usage. Since most programs use only a small part of
the allocated stack locations for interrupts and/or subrou-
tine stacking purposes, the unused bytes are usable for
program data storage. See Fig, 4 for details on stacking
order.
196 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ___

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CDP68HC05D2 전자부품, 판매, 대치품
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ 6805-Serles Microprocessors and Microcomputers
CDP68HC05D2 .
7
I
7
1
12
1 PC
12 6
101010101011111
A
X
0
1 Accumulator
0
1 Index Register
0
1 Program Counter
0
1 Stack Poi nter
Condition Code Register
Carry/Borrow
Zero
'--___ Negative
L-_ _ _ _ Interrupt Mask
L-_ _ _ _ _ Half Carry
Fig. 5 - Programming model.
II)
Increasing Memory
Addresses
7 o Stack
1 11 11 ICondition Code Register I
N
Accumulator
T
Index Register
~ DecreaSing Memory
R Addresses
01 0 10 1
PCH
U
PCL
P
T
Unstack
Note: Since the Stack POinter decrements dUring pushes. the PCl
IS stacked first. followed by PCH. etc Pulling from the stack IS In the
reverse order
Fig. 6 - Stacking order.
CPU Registers
The CDP68HC05D2 CPU contains five registers, as shown
in the programming model of Fig. 5. The interrupt stacking
order is shown in Fig. 6.
Accumulator (A)
The accumulator is an 8-blt general-purpose register used
to hold operands, results of the arithmetic calculations, and
data manipulations.
Index Register (X)
The x register is an 8-bit register which is used during the
indexed modes of addressing. It provides an 8-bit value
which is used to create an effective address. The index
register is also used for data manipulations with the read-
modify-write type of instructions and as a temporary stor-
age register when not performing addressing operations.
Program Counter (PC)
The program counter is a 13-bit register that contains the
address of the next instruction to be executed by the
processor.
Stack Pointer (SP)
The stack pointer is a 13-bit register containing the address
of the next free locations on the push-down/pop-up stack.
When accessing memory; the seven most significant bits
are permanently configured to 0000011. These seven bits
are appended to the six least significant register bits to
produce an address within the range of $OOFF to $OOCO. The
_______________________________________________________________ 199

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