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PDF CDP68HC68A2 Data sheet ( Hoja de datos )
| Número de pieza | CDP68HC68A2 | |
| Descripción | CMOS Serial 10-Bit A/D Converter | |
| Fabricantes | GE | |
| Logotipo |  |
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_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ CMOS Peripherals
Advance Information
CDP68HC68A2
OSC
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MOSI
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CE
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TOP VIEW
VDD
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TERMINAL ASSIGNMENT
CMOS Serial10-Bit AID Converter
Features:
• 10-bit resolution
• a-bit mode for single data byte transfers
• SPI (Serial Peripheral Interface) compatible
• Operates ratiometrically referencing VDD or
an external source
• 14/ls 1O-bit conversion time
• a multiplexed analog input channels
• Independent channel select
• Three modes of operation
• On chip oscillator
• Low power CMOS circuitry
• Intrinsic sample and hold
• 16-lead dua/-in-line plastic
package
• 20-lead dual-in-line small-
outline plastic package
The CDP68HC68A2 is a CMOS 8- or 10-bit successive
approximation analog to digital converter (A/D) with a
standard RCA/Motorola Serial Peripheral Interface (SPI)
bus and eighi multiplexed analog inputs Voltage
referencing is obtained from either the VDD pin or an
external precision reference forthe sacrifice of one channel
when enabled. The operating range of the converter includes
the entire VD D to Vss voltage range for each of the eight
inputs.
The CDP68HC68A2 implements a switched capacitor,
successive approximation A/D conversion technique which
provides an inherent sample-and-hold function. An on-chip
Schmitt oscillator provides the internal timing of the A/D
converter It can be driven by an external oscillator or
system clock in the external mode, orcan be connected to a
single external capacitor to provide an independent clock in
the internal mode. The minimum 10-bit converSion time per
input is 14-microseconds/channel. Each conversion in the
1O-bit mode requires 14 oscillator clock pulses where 12 are
required in the 8-bit mode allowing a 12-mlcrosecond/-
channel conversion time
A unique feature of the CDP68HC68A2 allows any
combination of the eight input channels to be selected and
converted in ascending channel order in anyone of three
modes. The mode selection enables single, multiple or
continuous channel conversion operation. The device has
three READ/WRITE registers which are used to select the
mode of operation, input channels, and starting address.
The 1O-bit conversion data is stored (right justified) in two
8-bit bytes. The most significant byte contains two status
bits which may be monitored by the microcomputer. An
8-bit mode is available which performs a faster eight bit
CE 6
SPI
CONTROL LOGIC
CONTROL
LOGIC
ADDRESS
CONTROL
LOGIC
SUCCESSIVE
APPROXIMATION
CONTROL LOGIC
10-81T CAPACITOR ARRAY
STATUS CONTROL
REGISTERS REGISTERS
·USED AS VOLTAGE INPUT IN EXTERNAL
REFERENCE MODE
Fig. 1 - Block diagram of the CDP68HC68A2.
File Number 1963
________________________________________________________ 521
1 page  
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ CMOS Peripherals
CDP68HC68A2
3.1 Device Addressing
To address the A/D registers internally, the A/D device first
needs to be addressed externally by the microcontroller
activating the Chip Enable of the A/D. After activating CE
the A/D device awaits SPI transfer cycles for phase I,
followed by phase II, see figure 3a and b for timing of the
Single Byte or Burst Modes of communication. Refer to
Note 1 for CEo
MISO always HI Impedance during Phase I, Phase II WRITE
operations and whan CE Islnacllve. Phase II READ operations will
have valid READ Data on the MISO.
CE ____~~----------~-----------
MOSI ~ Addr••• Byte
D'I'BYI'~
MISO---..HI-.Z :.;;,.:;-;-:.::.::.;-.--\ --<~~HI--Z-----
to be performed upon, see address map in appendix,
section 5.3 for register allocation. To follow are details on
bit descriptions.
BIT SIGNIFICANCE, most to least from left to right:
I I I I Io A4 A3 A2 A1
AO
Fig. 4 - Address/Control write byte.
ii/w (READ/WRITE)
This bit is used to control the data direction during the
following SPI REGISTER DATA ACCESS (Phase II cycles).
The bit is logically set HIGH or cleared LOW to initiate one
or more REGISTER DATA ACCESS - WRITE or READ
operations respectively. Either mode, once designated, will
be maintained until CE is deactivated and a new
ADDRESS/CONTROL WRITE (Phase I) is invoked.
UNUSED
Tran,'" Cycle:
Phl.e:
92CS-42556
II
(a) Single byte transfer.
(Requires 2 SPI transfers)
CE----Ir--------------~'_____
I . . IMOSI ~ Addr••• Byte
Oat, Byte 0.1.
D'ta ~
MISO
ADDRESS: WRITE ADDR:1
ADDR:1
••• ~
ADDR:2 ... ADDA:N
Tranlfer Cycle:
N+1
Ph. ., :
"II
92CS-42555
(b) Multiple (N) byte transfer.
(Efficient device communication requiring N+l SPI transfers)
Fig. 3 - Timing diagrams for (a) single byte transfer and
(b) multiple (N) byte transfer.
During the (N+1) 'th Burst Mode Transfer, the address
transferred will be N and is advanced internally to N+1 at the
completion of that cycle. For example, if the initial address
was 00 and N was desired to be 06, the address accessed in
the 7th burst mode transfer will be address 06, yet internally
the address will point to address 07 after transferring the
contents of 06, see section 3.1.1 for details on the
ADDRESS/CONTROL WRITE. The previous example
applies to Control, Status and selected consecutive Data
Registers. It does not apply to Data Registers which are not
selected since they are skipped entirely, or not consecutive
since the address is advanced more than an increment until
the next selected channel is addressed, see Note 5 on Data
Registers in Register allocation map, appendix, section 5.3.
3.1.1 ADDRESS/CONTROL WRITE (Phase I)
The two unused bits must be cleared to the logical LOW
state to address any of the internal registers of the
CDP68HC68A2.
An:
The five ADDRESS bits A4-AO are used to address the
registers in accordance with the address allocation table of
appendix, section 5.3. When addressing READ only Data
Registers it should be noted that when in 1O-bit mode, the
AO addresses the MOST/LEAST SIGNIFICANT DATA
REGISTER bytes when logically LOW and HIGH
respectively. In the 8-bit mode the data register bytes are
LOW byte only (Since there is no HIGH byte AO is a 'don't
care').
3.1.2 REGISTER DATA ACCESS (Phase II)
The ADDRESS/CONTROL WRITE in Phase I (one SPI
transfer cycle) is followed by REGISTER DATA ACCESS
during Phase II of the SPI transfers. This operation is either
a READ or a WRITE depending on the operation previously
deSignated by the ADDRESS/CONTROL WRITE byte. CE
determines whether Phase II is to be a Single Byte or Burst
transfer and when transfers terminate, see Note 1.
If CE is active for just one Phase II SPI transfer, it will only
be a Single Byte transfer; however, if it remains asserted
after the first Phase II SPI transfer, multiple byte transfers
will proceed to occur. This is the Burst Mode. While in this
mode, the address written in Phase I is incremented
automatically at the completion of each,register access.
The CONTROL and STATUS Registers are accessed
directly, and advanced by Single address increments. Data
Registers are advanced to the NEXT selected channel in the
CSR. See Note 5 for limitations of Data and Control/Status
accesses.
4. Control and Stalus Registers
There are three READ/WRITE control registers and one
READ only STATUS Register in the CDP68HC68A2. They
are described in detail here and shown in the register
allocation table in appendix section 5.3.
The ADDRESS/CONTROL WRITE phase is a dual purpose 4.1 Mode Select Regllter (MSR)
WRITE only operation that performs register addressing
and READ/WRITE control. Phase I is invoked by the first
A(~;~o~~~oool I I I I liE I I ISPI Transfer at the onset of activated CEo Both address and
X X ExT VA Me
M1 MO
control are performed using eight bits, refer to figure 4 for
bit descriptions. One of these bits (MSB) is used to This READ/WRITE register is used to select the mode of
deSignate READ or WRITE Phase II operations to follow. operation as well as various functions of the device. Data is
The remaining seven bits are used to deSignate a register maintained in this register until new data is written, initially
address of which the following READ or WRITE operation is powers up with all bits cleared to logical zero. A WRITE to
__________________________________th_e_M_S_R_w_il_l c_le_ar_t_he_I_N_T _ou_tp_u_t a_n_d_a_ll S_T_A_T_US__bits5.25
4
5 Page 
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ CMOS Perlpherala
5.3.1.1 Oete Regl.ter Acce••
After invoking conversions in any mode without hardware
interrupts, deassertion of CE will be necessary to read the
STATUS Register then again to address the Data Registers.
Converted Digital Data is retrieved (and validated in 10-bit
mode only) from the Data Registers. After a conversion is
complete or terminated, the Starting Address (which should
have been a selected channel) should be the first Data
Register address read. The SAR can initially be setto any of
the selected channels to affect the order in which the
channel data is retrieved.
5.3.1.1.1 10-blt Mode
In the 10-bit mode. two data registers are associated with
each analog input channel. Upon completion of the first
conversion. the data is internally stored at the addresses
designated by the CAR written in the SAR before converting.
The most Significant Byte (MSB) contains the two status
bits and the two most significant bits of the 10-bit AID
conversion data. The eight least significant data bits are
stored in the Least Significant Byte (LSB). These sixteen
registers are read only registers.
The following is the format of the Data Registers in the
10-bit Mode (refer to the register allocation table in
appendIx, section 5.3.1):
ADDRESS: 1DVO 1DOVO 1 0
OOOOOOOO(MSB)
10
1
0
0 D9 D8
IADDRESS:
D7
00000001 (LSB)
D6 ID51 D41 D3 D2 D1 DO
CDP68HC68A2
OOVn (Oete Overrun)
This status bit is set to a logical HIGH level upon completion
of a data conversion to a channel already containing valid
data which has not been read. It indicates whether or not the
previous data has been overwritten. The bit is reset LOW by
reading the register or performing a WRITE to the MSR,
CSR or both.
5.3.1.1.2 8-blt t.'!ode
In the 8-bit mode, an 8-bit conversion is performed on the
selected channels and stored in the corresponding data
register. The status bits associated with Data Registers in
the 10-bit mode are not included in the 8-bit mode, thus the
STATUS REGISTER must be monitored to determine the
status of the conversions. Since the conversion data is
stored in a single 8-bit byte in the 8-bit mode, the data for
each channel can be obtained with a single read cycle, as
compared to two read cycles required in the 10-bit mode.
The K.1OSf/LEAST bit is a don't care when written to in the
8-bit mode. When reading the Data Registers in the burst
mode, the address is automatically incremented to the next
selected channel. The read sequence should be complete,
see Note 2.
The following is the format of the Data Registers in the 8-bit
Mode:
ADDRESS:
0000111X
I1 07 1 D6 1D51 04 1 D3 1 D2 I D1 1 DO
lEI
ADDRESS.
OOOOOOOX
I1 D7 1 D6 1D51 04 1 D3 1 D2 1 D1 I DO
I I IADDRESS:
00001110(MSB). DV7 , DOV7 . 0
I0
I
0
0 D9 D8
IADDRESS:
D7
00001111 (LSB)
DB I D51 D41 D3 D2 D1 DO
The bits in these registers are described here In more detail:
OVn (Oete Velld)
This status bit is used to determine the validity of the
conversion stored in the data data register. The DV bit is set
HIGH upon completion of an AID conversion to the
corresponding channel. The bit is reset to a logical LOW
level when the register is read (see Note 4), or if the MSR,
CSR, or SAR is written to. It is also posslbleforthe DV bitto
be reset if an abort condition arises while a register is being
loaded.
On (Oete bits)
These ten data bits represent the 1O-bit conversion data for
the corresponding input channel. The bits are stored (Right
Justified) In the two, corresponding eight bit bytes upon
completion of the conversion. The data Is maintained in the
register only until another conversion is completed.
The bits in these registers are described here in more detail:
On (Oete bit.)
These eight data bits represent the 8-bit conversion data for
the corresponding input channel. The bits are stored in a
single eight bit byte upon completion of the conversion.
The data is maintained in the register only until another
conversion Is completed.
5.3.1.1.3 Oete Recovery Exemple.
A general method of implementation for any mode, single
transfer or burst transfer is to build external software
counter routines in the microcontroller. This method can
require more code for more sophisticated designs, but
works well when multiple modes are used. In this manner,
channel activity in the CDP68HC68A2 is reconstructed for
the requesting of appropriate channels within the device.
For Mode 1, a STATUS Register polling routine can wait for
proper completion, then yield the next address to be
converted (channel in CAR) for antiCipation of channel
Data Register Address to follow.
A simple method 11'1 mode 2 Is to load the SAR with the
lowest enabled channel then retrieve data beginning with
that same address. Continue Phase II implementing the
burst mode anticipating the rest of the selected channels to
follow. For example CSR =AA, SAR =92 read back channels
1, 3, 5, 7 In the Burst Mode beginning with address 02
(Channell). Fou~ c,hannels are converted then read back.
Counting the number of CSR bits can determine total
number of channels to retrieve.
_________________________________________________________________ 531
11 Page | ||
| Páginas | Total 13 Páginas | |
| PDF Descargar | [ Datasheet CDP68HC68A2.PDF ] | |
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