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PDF IT8888G Data sheet ( Hoja de datos )
| Número de pieza | IT8888G | |
| Descripción | PCI-to-ISA Bridge Chip | |
| Fabricantes | ITE | |
| Logotipo |  |
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IT8888G
PCI-to-ISA Bridge Chip
(Code Name: Golden Gate)
Preliminary Specification V0.9
ITE TECH. INC.
Specification subject to Change without notice, AS IS and for reference only. For purchasing, please contact
sales representatives.
1 page  
Contents
CONTENTS
1. Features ....................................................................................................................................................... 1
2. General Description ....................................................................................................................................... 3
3. Pin Configuration ........................................................................................................................................... 5
4. Pin Description............................................................................................................................................... 7
5. Functional Description ................................................................................................................................. 13
5.1 PCI Slave Interface ........................................................................................................................... 13
5.2 PCI Master Interface ......................................................................................................................... 13
5.3 PCI Parity .......................................................................................................................................... 14
5.4 Positively Decode Spaces ................................................................................................................ 14
5.5 Subtractive Decode........................................................................................................................... 14
5.6 PC/PCI DMA (PPDMA) Slave Controller .......................................................................................... 14
5.7 Distributed DMA (DDMA) Slave Controller ....................................................................................... 15
5.8 Type-F DMA Timing .......................................................................................................................... 15
5.9 ISA Bus I/O Recovery Time .............................................................................................................. 15
5.10 ISA Bus Arbiter.................................................................................................................................. 15
5.11 SMB Boot ROM Configuration .......................................................................................................... 16
5.12 Serialized IRQ ................................................................................................................................... 18
5.13 NOGO and CLKRUN# ...................................................................................................................... 18
5.14 Optional FLASH ROM Interface........................................................................................................ 19
5.15 Testability .......................................................................................................................................... 19
6. Register Description..................................................................................................................................... 21
6.1 Configuration Register Map .............................................................................................................. 21
6.2 Access Configuration Registers........................................................................................................ 22
6.3 Configuration Registers Description ................................................................................................. 24
6.3.1 Device/Vendor ID Register................................................................................................... 24
6.3.2 Status / Command Register ................................................................................................. 24
6.3.3 Class Code/ Revision ID Register ........................................................................................ 25
6.3.4 Header Type/ Primary MLT/ Cache Line Size Register ....................................................... 26
6.3.5 Subsystem Device/Vendor ID Register................................................................................ 26
6.3.6 DDMA Slave Channel_1 Register / DDMA Slave Channel_0 Register ............................... 26
6.3.7 DDMA Slave Channel_3 Register / DDMA Slave Channel_2 Register ............................... 27
6.3.8 DDMA Slave Channel_5 Register / DMA Type-F Timing / PPD Register............................ 28
6.3.9 DDMA Slave Channel_7 Register / DDMA Slave Channel_6 Register ............................... 29
6.3.10 ROM / ISA Spaces and Timing Control................................................................................ 29
6.3.11 Retry/Discard Timers, Misc. Control Register ...................................................................... 31
6.3.12 Positively Decoded IO_Space_0 Register ........................................................................... 33
6.3.13 Positively Decoded IO_Space_1 Register ........................................................................... 33
6.3.14 Positively Decoded IO_Space_2 Register ........................................................................... 34
6.3.15 Positively Decoded IO_Space_3 Register ........................................................................... 34
6.3.16 Positively Decoded IO_Space_4 Register ........................................................................... 35
6.3.17 Positively Decoded IO_Space_5 Register ........................................................................... 35
6.3.18 Positively Decoded Memory_Space_0 Register .................................................................. 35
6.3.19 Positively Decoded Memory_Space_1 Register .................................................................. 36
6.3.20 Positively Decoded Memory_Space_2 Register .................................................................. 36
6.3.21 Positively Decoded Memory_Space_3 Register .................................................................. 37
6.3.22 Undefined Register............................................................................................................... 37
6.4 DDMA Slave Registers Description .................................................................................................. 38
7. Characteristics ............................................................................................................................................. 41
7.1 DC Electrical Characteristics ............................................................................................................ 42
7.2 AC Characteristics ............................................................................................................................ 43
7.3 Waveforms ........................................................................................................................................ 46
8. Package Information .................................................................................................................................... 61
www.ite.com.tw
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IT8888G V0.9
5 Page 
General Description
2. General Description
The IT8888G is a PCI to ISA bridge single function device. The IT8888G serves as a bridge between the PCI bus
and ISA bus. The IT8888G’s 32-bit PCI bus interface is compliant with PCI Specification V2.1 and supports both
PCI Bus Master & Slave. The PCI interface supports both programmable positive and full subtractive decoding
schemes.
The IT8888G also integrates two enhanced DMA Slave controllers for achieving PCI DMA cycles: PC/PCI DMA
Slave Controller & Distributed DMA Slave Controllers.
The IT8888G also implements the optional fast positive decode of F, E, D, C memory segments. This special
feature can provide a direct connection to an FALSH boot ROM.
The NOGO function, which is also implemented in the IT8888G for enabling or disabling subtractive decode of PCI
interface, could be a software controlled output pin from other host controlled devices. The Serial IRQ is also
implemented in the device for sending and receiving ISA IRQs & IOCHCK#. The device includes an ISA interface
which supports full ISA compatible functions.
The IT8888G is available in 160-pin TFBGA package.
www.ite.com.tw
3
IT8888G V0.9
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet IT8888G.PDF ] | |
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