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부품번호 | MWS5101 기능 |
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기능 | 256-Word by 4-Bit LSI Static Random-Access Memory | ||
제조업체 | GE | ||
로고 | |||
전체 6 페이지수
Random-Access Memories (RAMs) _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
MWS5101
A3
A2
AI
AD
A5
AS
A7
VSS
OJ: I
001
012
I 22
2 21
~ 20
4 19
5 18
S 17
7 16
8 15
9 14
10 13
II 12
TOP VIEW
vOO
A4
rRlnW
QO
CS2
004
OI4
003
OI3
DO~
92CS-29976RI
TI;RMINAL ASSIGNMENT
256-Word by 4-Bit LSI Static
Random-Access Memory
Features:
• Industry standard pinout
• Output-Disable for common I/O systems
• Very low operating current-8 mA • 3-state data output for bus-oriented
= =at Voo 5 V and cycle time 1 ps
systems
• Two Chip-Select inputs-simple
• Separate data inputs and outputs
memory expansion
• Memory retention for standby battery
voltage of 2 V min
The RCA-MWS5101 is a 256-word by 4-bit static random-
access memory designed for use In memory systems where
high speed, very low operating current, and simplicity in
use are desirable. It has separate data inputs and outputs
and utilizes a single power supply of 4 to 6.5 volts.
Two Chir·Select inputs are provided to simplify system
expansion. An Output Disable control provides Wire-OR
capability and is also useful in common Input/Output
systems by forcing the output into a high-impedance state
during a write operation independent of the Chip-Select
input condition. The output assumes a high-impedance
state when the Output Disable is at high level or when the
chip is deselected by CS1 and/or CS2.
The high noise immunity of the CMOS technology is
preserved in this design. For TTL interfacing at 5-V
operation, excellent system noise margin is preserved by
using an external pull-up resistor at each input.
For Rpplications requiring wider temperature and operating
voltage ranges, the mechanically and functionally equivalent
static RAM, RCA-CDP1822, may be used
The MWS5101 types are supplied in 22-lead hermetic dual-
in-line, side-brazed ceramic packages (0 suffix), in 22-lead
dual-in-line plastic packages (E suffix), and in chip form (H
suffix).
OPERATIONAL MODES
MODE
READ
WRITE
WRITE
STANDBY
STANDBY
OUTPUT DISABLE
CIiTP Select 1
CS1
0
0
0
1
X
X
INPUTS
Chip Select 2 Output Disable
CS2 00
10
10
11
XX
0X
X1
Logic 1 = High
Logic 0 = Low
X = Don't Care
Read/Write
R/VI
1
0
0
X
X
X
OUTPUT
Read
Data In
High Impedance
High Impedance
High Impedance
High Impedance
I
File Number 1106
686 ___________________________________________________________
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Random-Access Memories (RAMs)
MWS5101
DYNAMIC ELECTRICAL CHARACTERISTICS at TA = 0 to 700 C, VDD = 5 V ±5%,
tr,tf= 20ns, VIH= 0.7 VDD, VIL = 0.3 VDD, CL = 100pF
CHARACTE RISTIC
Write Cycle Times (Fig. 2)
Write Cycle
Address Setup
Write Recovery
Write Width
Input Data
Setup Time
i Data In Hold
Chip·Select 1
twc
tAS
tWR
tWRW
tDS
tDH
Setup
Chip·Select 2
tCS1S
Setup
tCS2S
Chip-Select 1 Hold tCS1H
Chip-Select 2 Hold tCS2H
Output Disable
Setup
to OS
LIMITS
MWS5101D, MWS5101E
L2 Tvpes
L3 Types
Min.t Typ.- Max. Min.t Typ~ Max
U
N
I
T
S
300 -
110 -
40 -
150 -
150 -
40 -
110 -
110 -
0-
0-
110 -
- 400 -
- 150 -
- 50 -
- 200 -
- 200 -
- 50 -
- 150 -
- 150 -
- 0-
-0-
- 150 -
-
-
-
-
-
- ns
-
-
-
-
-
t Time required bV a limit deVice to allow for the indicated function
- TYPical value. are for T A = 25aC and nominal V DO
~I·~------------twc
AO-A7
CHIp-sELECT 1
CHIP- SELECT 2
OUTPUT DISABLE
011- 014
READ/WRITE
'CSIH
tCS2H
'os
'WRW----~J~--~----
~DON'TCARE
* 'ODS IS REQUIRED FOR COMMON I/O
OPERATION ONLY, FOR SEPARATE J:lO
OPERATIONS, OUTPUT DISABLE IS DON'T CARE
tZCN ... 30804R4
Fig. 2 - WrIte cycle timing waveforms.
------_________________________________________________________ 689
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부품번호 | 상세설명 및 기능 | 제조사 |
MWS5101 | 256-Word by 4-Bit LSI Static Random-Access Memory | GE |
MWS5101 | 256-Word x 4-Bit LSI Static RAM | Intersil Corporation |
DataSheet.kr | 2020 | 연락처 | 링크모음 | 검색 | 사이트맵 |