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PDF MWS5101A Data sheet ( Hoja de datos )
| Número de pieza | MWS5101A | |
| Descripción | 256-Word by 4-Bit LSI Static Random-Access Memory | |
| Fabricantes | GE | |
| Logotipo |  |
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Random-Access Memories (RAMs) _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
MWS5101A
A3
A2
AI
AO 4
A5 5
A6
07
V55
01 I
8
9
001 -10
Dr2
II
22
21
20
19
18
17
16
15
14
13
12
TOP VIEW
VDD
A4
R/W
CSf
o0
CS2
004
Dr4
003
DB
002
9ZCS-29976RI
TERMINAL ASSIGNMENT
256-Word by 4-Bit LSI Static
Random-Access Memory
Features:
• Industry standard Pinout
• TTL compatible
• Very low operating current-B mA
at Voo = 5 V and cycle time = 1 iJS
• Output-Disable for common I/O systems
• 3-state data output for bus-oriented
• Two Chip-Select Inputs-simple
systems
memory expansion
• Separate data inputs and outputs
• Memory retention for standby battery
voltage of 2 V min.
The RCA-MWS51 01 A IS a 256-word by 4-blt static random-
access memory designed for use in memory systems where
high speed, very low operating current, and simplicity In
use are desirable It has separate data inputs and outputs
and utilizes a single power supply of 4 to 6 5 volts.
Two Chip-Select Inputs are provided to simplify system
expansion. An Output Disable control provides Wire-OR
capability and is also useful in common Input/Output
systems. The Output Disable input allows these RAM's to be
used in common data Input/Output systems by forcing the
output into a high-impedance state during a write operation
Independent of the Chip-Select Input condition. The output
assumes a high-impedance state when the Output Disable
is at high level or when the chip is deselected by CSI and/or
CS2
For applications requiring CMOS compatibility over wider
operating voltage and temperature ranges, the mechanical
and functional equivalent RCA-CDPI822 static RAM may
be used
The MWS5101A types are supplied in 22-lead hermetic
dual-in-line, side-brazed ceramic packages (0 suffix). in
22-lead dual-in-line plastic packages (E suffix), and in chip
form (H suffix).
OPERATIONAL MODES
INPUTS
MODE
READ
WRITE
WRITE
STANDBY
STANDBY
OUTPUT DISABLE
Chip Select 1
CS1
a
a
a
1
X
X
Chip Select 2
CS2
1
1
1
X
a
X
Output Disable
00
a
a
1
X
X
1
Logic 1 = High
aLogic = Low
X = Don't Care
Read/Write
R/W
1
a
a
X
X
X
OUTPUT
Read
Data In
High Impedance
High Impedance
High Impedance
High Impedance
File Number 1207
692 ______________________________________________________________
1 page  
Random-Access Memories (RAMs) _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
MWS5101A
DATA RETENTION CHARACTERISTICS at TA = 0 to 70" C; See Fig. 3.
CHARACTERISTIC
Minimum Data
Retention Voltage,
Data Retention
Quiescent
Current, 100
VOR
L2Types
L3Types
Chip Deselect to Data
Retention Time,
~OR
Recovery to Normal
Qperation Time,
~
VOO to VOR Rise and
Fall Time
tr,tf
TEST
CONDITIONS
VDR
(V)
VDD
(V)
--
2
-
-
-5
-5
25
LIMITS
All Types
UNITS
Min. Typ. Max.
- 1.5 2 V
-
-
2
5
10
50
,..A
600 - -
ns
600 - -
1 - - ,..s
= r·TYPlcal values are for TA 25 ·C.
DATA RETENTION
MODE
V-"D,,-D_ _":!I..
O~V~D O~D ~'r'CDR
VDR
'Re
eS2
ViH\; I
VIL~
I fViH
¥ V1L 92CS-30e05RI
Fig. 3 - Low Voo data retention tlmmg waveforms
!
I
WRITE
ADDRESS
DECODER
:!.
I
READ
ADDRESS
DECODER
Voo
92CS -272 56R2
Fig. 4 - Memory cell configuration
696 _____________________________________________________________
5 Page | ||
| Páginas | Total 6 Páginas | |
| PDF Descargar | [ Datasheet MWS5101A.PDF ] | |
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