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PDF CDP1833BC Data sheet ( Hoja de datos )
| Número de pieza | CDP1833BC | |
| Descripción | CMOS 1024-Word x 8-Bit Static Read-Only Memory | |
| Fabricantes | GE | |
| Logotipo |  |
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Read-Only Memories (ROMs) _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
CDP1833, CDP1833C, CDP1833BC
MA7
MA6
MAO
MA4
MA3
MA2
MAl
MAO
BUS 0
BUSt
BUS2
vSS
24
23
3 22
4 21
5 2C
6 19
7 18
8 17
9 16
10 15
" 14
12 13
TOP VIEW
vOO
TPA
cn
CSI
CS2
MRD
CEO
BUS7
BUS6
eUS5
BUS4
BUS3
92CS- 2S8S9R2
TERMINAL ASSIGNMENT
CMOS 1024-Word X 8-Bit Static
Read-Only Memory
Features:
• CDP1833BC is compatible with the CDP1802BC 5 MHz microprocessor
• On-chip address latch
• Interfaces with CDP1800-series microprocessors without additional
components
• Optional programmable location within 64K memory space
• Three-state outputs
The RCA-CDP1833, CDP1833C, and CDP1833BC are static
8192-bit mask-programmable CMOS read-only memories
organized as 1024-words x 8 bits and are completely static;
no clocks are required. They will directly interface with the
CDP1800-series microprocessors without additional
comoonents.
The CDP1833, CDP1833C, and CDP1833BC respond to a
16-bit address multiplexed on 8 address lines. Address
latches are provided on-chip to store the 8 most significant
bits of the 16-bit address. By mask option, this ROM can be
programmed to operate in any 1024-word block within 64K
memory space. The polarity of the high-address strobe
(TPA), CEI, CS1, and CS2 are user mask-programmable.
The Chip-Enable output signal (CEO) is "high" when the
device is selected. Terminals CEO and CEI can be
connected in a daisy chain to control selection of RAM
memory in a microprocessor system without additional
components.
The CDP1833C and CDP1833BC are functionally identical
to the CDP1833. The CDP1833 has a recommended
operating voltage range of4 to 10.5 volts, and the CDP1833C
and CDP1833BC have a recommended operating voltage
range of 4 to 6.5 vol~s. The CDP1833BC is designed to
interface with the CDP1802BC microprocessor.
The CDP1833, CDP1833C, and CDP1833BC are supplied
in 24-lead hermetic dual-in-line side-brazed ceramic
package (D suffix) and 24-lead dual-in-line plastic package
(E suffix). The CDP1833C IS also available In chip form (H
suffix).
"
" CD~9~3'3
~
lt2..
I
ADDR BUS
TPA
------
-----
RAM
MRD --
CEO
ADDR BUS
TPA
MRD
MWR
l~
NO-N2 MRD
TPB
r--- Q
CPU
CDPl800
SERIES
SCO SCI
INTERRUPT
DMA-IN O=T
EFI-EF4
II II
8-BIT BIDIRECTIONAL DATA BUS
Fig. 1 - Typical CDP1800 Seri6s microprocessor system.
i'r~
I/O
CONTROL
II
'2CM-2lI890RI
File Number 1135
734 __________________________________________________
1 page  
Read-Only Memories (ROMs) _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
CDP1833, CDP1833C, CDP1833BC
Note:
The dynamic characteristics and timing diagrams indicate
maximum performance capability of the CDP1833. When
used di rectly with a CDP1800-series microprocessor, ti ming
will be determined by the clock frequency and internal
delays of the microprocessor.
The following general timing relationships will hold when
the CDP1833 is used with a CDP1800-series micro-
processor.
tAH = 0.5 te
tPAW = 1 te
MRD occurs one clock period (te) earlier than the address
bits MAO-MA7.
where te = - - - - - - -
CPU clock frequency
738 __________________________________________________
5 Page | ||
| Páginas | Total 5 Páginas | |
| PDF Descargar | [ Datasheet CDP1833BC.PDF ] | |
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