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PDF MG82FG5A64 Data sheet ( Hoja de datos )
| Número de pieza | MG82FG5A64 | |
| Descripción | 8051-Based MCU | |
| Fabricantes | Megawin | |
| Logotipo |  |
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8051-Based MCU
MG82FG5A64
Data Sheet
Version: A2.4
This document contains information on a new product under development by Megawin. Megawin reserves the right to change or
discontinue this product without notice.
Megawin Technology Co., Ltd. 2005 All rights reserved.
2015/09 version A2.4
1 page  
Content
Features............................................................................................................. 3
Content .............................................................................................................. 5
1. General Description ..................................................................................... 10
2. Block Diagram ............................................................................................. 11
3. Special Function Register ............................................................................ 12
3.1. SFR Map (Page 0~F) ...................................................................................................12
3.2. SFR Bit Assignment (Page 0~F)...................................................................................14
3.3. Auxiliary SFR Map (Page P) .........................................................................................17
3.4. Auxiliary SFR Bit Assignment (Page P) ........................................................................18
4. Pin Configurations ....................................................................................... 19
4.1. Package Instruction ......................................................................................................19
4.2. Pin Description .............................................................................................................21
4.3. Alternate Function Redirection......................................................................................24
5. 8051 CPU Function Description................................................................... 26
5.1. CPU Register ...............................................................................................................26
5.2. CPU Timing ..................................................................................................................27
5.3. CPU Addressing Mode .................................................................................................28
6. Memory Organization .................................................................................. 29
6.1. On-Chip Program Flash................................................................................................29
6.2. On-Chip Data RAM.......................................................................................................30
6.3. On-chip expanded RAM (XRAM)..................................................................................34
6.4. External Data Memory access ......................................................................................35
6.4.1.
Multiplexed Mode for 8-bit MOVX .........................................................................................36
6.4.2.
Multiplexed Mode for 16-bit MOVX .......................................................................................37
6.4.3.
No Address Phase Mode for MOVX .....................................................................................38
6.5. Declaration Identifiers in a C51-Compiler .....................................................................39
7. Dual Data Pointer Register (DPTR) ............................................................. 40
8. System Clock............................................................................................... 41
8.1. Clock Structure.............................................................................................................41
8.2. Clock Register ..............................................................................................................42
8.3. System Clock Sample Code .........................................................................................45
9. Watch Dog Timer (WDT) ............................................................................. 48
9.1. WDT Structure..............................................................................................................48
9.2. WDT During Idle and Power Down ...............................................................................48
9.3. WDT Register...............................................................................................................49
9.4. WDT Hardware Option .................................................................................................50
9.5. WDT Sample Code.......................................................................................................51
10.System Reset .............................................................................................. 53
10.1.
10.2.
10.3.
10.4.
10.5.
10.6.
10.7.
10.8.
Reset Source................................................................................................................53
Power-On Reset ...........................................................................................................53
External Reset..............................................................................................................54
Software Reset.............................................................................................................54
Brown-Out Reset ..........................................................................................................55
WDT Reset...................................................................................................................55
Illegal Address Reset....................................................................................................55
Reset Sample Code .....................................................................................................56
11.Power Management..................................................................................... 57
11.1. Brown-Out Detector......................................................................................................57
11.2. Power Saving Mode .....................................................................................................58
11.2.1. Slow Mode ............................................................................................................................58
11.2.2. Sub-Clock Mode ...................................................................................................................58
MEGAWIN
MG82FG5A64 Data Sheet
5
5 Page 
2. Block Diagram
Figure 2–1. Block Diagram
XTAL1(P6.1)
XTAL2(P6.0/CKO)
ALE(P4.6)
nWR(P3.6)
nRD(P3.7)
nINT0(P3.2)
nINT1(P3.3)
nINT2(P4.3)
nINT3(P4.2)
RXD0(P3.0)
TXD0(P3.1)
RXD1(P1.2)
TXD1(P1.3)
T0/T0CKO(P3.4)
T1/T1CKO(P3.5)
T2/T2CKO(P1.0)
T2EX(P1.1)
T3/T3CKO(P0.1)
T3EX(P0.0)
ECI(P2.1)
CEX0~CEX5
(P2.2~P2.7)
AIN0~AIN7
(P1.0~P1.7)
KBI0~KBI7
(P0/P2/P5/P6)
nSS(P1.4)
MOSI(P1.5)
MISO(P1.6)
SPICLK(P1.7)
TWI_SCL(P4.0)
TWI_SDA(P4.1)
XTAL
OSC
Clock
Multiplier
IHRCO
11.059
MHz
ILRCO
32KHz
8051 CPU (1T)
Ext. INT
UART0
UART1
Timer0
Timer1
Timer2
Timer3
PCA
Timer
12-bit ADC
Keypad Int.
SPI
TWSI
WDT
OCD
Interface
Flash
64K X 8
RAM
256 X 8
XRAM
5120 X 8
ISP/IAP
Port0
Port1
Port2
Port3
Port4
Port5
Port6
BOD0
BOD1
RST
OCD_SCL
OCD_SDA
P0.0~P0.7
P1.0~P1.7
P2.0~P2.7
P3.0~P3.7
P4.0~P4.6
P5.0~P5.7
P6.0~P6.7
MEGAWIN
MG82FG5A64 Data Sheet
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet MG82FG5A64.PDF ] | |
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